67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/**
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* \file
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* \brief Physical address map for Cavium ThunderX CN88xx SoCs
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*/
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/*
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* Copyright (c) 2017 ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* See Cavium CN88xx Hardware Manual 2.55P, in particular Chapter 4
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*/
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#ifndef CN88XX_MAP_H
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#define CN88XX_MAP_H
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/*
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* DRAM/L2 cached memory
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*/
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#define CN88XX_MAP_LMC_OFFSET 0x0000000000000000UL
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#define CN88XX_MAP_LMC_MASK 0x000000FFFFFFFFFFUL
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/*
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* Converting a base address to a CCPI-node address
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*/
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#define CN88XX_MAP_LMC_CCPI_OFFSET(_ccpi,_a) \
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(((_ccpi & 0x3) << 40) | ((_a) & CN88XX_MAP_LMC_MASK))
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#define CN88XX_MAP_IO_CCPI_OFFSET(_ccpi,_a) \
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(((_ccpi & 0x3) << 44) | (_a))
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/*
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* I/O spaces
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*/
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#define CN88XX_MAP_NCB_OFFSET 0x800000000000UL
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#define CN88XX_MAP_RSL_OFFSET 0x87E000000000UL
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#define CN88XX_MAP_AP_OFFSET 0x87F000000000UL
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#define CN88XX_MAP_SLI_OFFSET 0x880000000000UL
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/*
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* Devices
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*/
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/*
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* UARTs
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*/
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#define CN88XX_MAP_UART0_OFFSET 0x87E024000000UL
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#define CN88XX_MAP_UART0_MSIX 0x87E024F00000UL
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#define CN88XX_MAP_UART1_OFFSET 0x87E025000000UL
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#define CN88XX_MAP_UART1_MSIX 0x87E025F00000UL
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/*
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* The GIC
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*/
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#define CN88XX_MAP_GIC_GICD_OFFFSET 0x801000000000UL
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#define CN88XX_MAP_GIC_CCS_OFFSET 0x801000010000UL
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#define CN88XX_MAP_GIC_CCS_SIZE 0x000000010000UL
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#define CN88XX_MAP_GIC_GITS_OFFSET 0x801000020000UL
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#define CN88XX_MAP_GIC_GICRX_OFFSET 0x801080000000UL
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#endif /* CN88XX_MAP_H */
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