251 lines
12 KiB
Plaintext
251 lines
12 KiB
Plaintext
/*
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* Copyright (c) 2013, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstr 6, CH-8092 Zurich.
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_cortex_m3_nvic.dev
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*
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* DESCRIPTION: Nested vectored interrupt controller for the cortex-m3 on pandaboard
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* This also contains control registers for SysTick
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*
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* This is derived from:
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*
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* [1] ARM Cortex M3 TRM (chapter 8)
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* [2] OMAP4460 TRM rev Y (chapter 17)
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* [3] ARMv7-M Architecture reference manual
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*
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* TODO: some registers are write-to-clear, and one needs a byteflip-on-write (really weird)
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* is there a mackerel keyword for those?
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*/
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device omap44xx_cortex_m3_nvic msbfirst (addr base)
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"Cortex-m3 Nested Vectored Interrupt Controller"
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{
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//nothing at offset 0
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register ICTR ro addr(base, 0x4) "Interrupt Controller Type" {
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_ 27;
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intlinesnum 5 "max. num. (N) interrupts supported 32(N+1)";
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};
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//SysTick registers
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register SYSTICK_CTRL rw addr(base, 0x10) "SysTick control and status register"{
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_ 15;
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countflag 1 rc "Reads 1 if timer counted to 0 since last read. Clears on read.";
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_ 13;
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clksource 1 "clock source: 1 = core clock, 0 = external reference clock";
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tickint 1 "interrupt on counting to 0";
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enable 1 "counter running (multishot)";
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};
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register SYSTICK_RV rw addr(base, 0x14) "SysTick reload value register"{
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_ 8;
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reload 24 "value to load into current value register when counter reaches 0 (N+1 clock pulses between countdowns)";
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};
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register SYSTICK_CRTV rw addr(base, 0x18) "SysTick current value register"{
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_ 8;
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current 24 rwc "current counter value, clears on write";
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};
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register SYSTICK_CALV ro addr(base, 0x1C) "SysTick calibration value register"{
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noref 1 "no reference clock provided";
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skew 1 "calibration value not exactly 10ms because of clock frequency";
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_ 6;
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tenms 24 "reload value for 10ms timing. 0 = value not known";
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};
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// Do not read 16 Bit values, only 32 bit ones, otherwise the
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// Mackerel code will crash on the PandaBoard
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regarray ISER addr(base, 0x100) [32] "Interrupt Set-Enable"
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type(uint32);
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regarray ICER addr(base, 0x180) [32] "Interrupt Clear-Enable"
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type(uint32);
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regarray ISPR addr(base, 0x200) [32] "Interrupt Set-Pending"
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type(uint32);
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regarray ICPR addr(base, 0x280) [32] "Interrupt Clear-Pending"
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type(uint32);
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regarray ABR ro addr(base, 0x300) [32] "Interrupt Active Bit"
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type(uint32);
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regtype priority_reg "Interrupt priority register" {
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prio_off3 8 rw "Priority, byte offset 3";
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prio_off2 8 rw "Priority, byte offset 2";
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prio_off1 8 rw "Priority, byte offset 1";
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prio_off0 8 rw "Priority, byte offset 0";
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};
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regarray IPR addr(base, 0x400) [31] "Priority Level"
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type(priority_reg);
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register CPUID_BASE ro addr(base, 0xD00) "CPU ID base register"{
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implementer 8 "implementer code. ARM is 0x41";
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variant 4 "implementation defined variant number";
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constant 4 "reads as 0xF";
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partno 12 "number of processor within family. cortex-m3 reads as 0xC23";
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revision 4 "implementation defined revision number";
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};
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register ICSR rw addr(base, 0xD04) "Interrupt Control State register"{
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nmipendset 1 "set pending NMI. since NMI has highest priority, it is activated immediatedly";
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_ 2;
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pendsvset 1 "set pending pendSV bit";
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pendsvclr 1 "clear pending pendSV bit";
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pendstset 1 "set pending SysTick bit";
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pendstclr 1 "clear pending SysTick bit";
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_ 1;
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isrpreemt 1 "Debug bit. pending interrupt will become active in next cycle";
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isrpending 1 "Interrupt pending bit. Excludes NMI and faults";
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vectpending 10 "ISR number of highest priority pending interrupt";
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rettobase 1 "no other active exceptions apart from current one";
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_ 2;
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vectactive 9 "active ISR number, as indexed in vectortable (external interrupts start at 16)";
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};
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register VTOR rw addr(base, 0xD08) "Vector Table offset register"{
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_ 2;
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tblbase 1 "0 = vector table base is 0x0, 1 = vector table is 0x20000000";
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tbloff 22 "Offset of vector table from base (bits 28..7 of offset only)";
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_ 7;
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};
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register AIRCR rw addr(base, 0xD0C) "Application interrupt and reset control register"{
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vectkey 16 "Reads as 0xFA05, must always(!) be written as 0x05FA"; //XXX: does mackerel have a way to enforce this weird condition?
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endianess 1 "1 = big endian, 0 = little endian. cannot be changed after reset";
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_ 4;
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prigroup 3 "interrupt priority grouping. (N+1) bits of interrupt priority can be used as a subpriority (will not preempt each other while active)";
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_ 5;
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sysresetreq 1 "signals outer system that reset is requested";
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vectclractive 1 "clear active vector. write 1 to clear all state information for active interrupts (including NMI and faults). Does not clear ISPR.";
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vectreset 1 "write 1 to reset system.";
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};
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register SCR rw addr(base, 0xD10) "System Control register"{
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_ 27;
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sevonpend 1 "make processor wake from WFE when interrupt changes from inactive to pending";
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_ 1;
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sleepdeep 1 "1 = indicate to system that processor clock can be stopped";
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sleeponexit 1 "sleep when returning from handler to thread mode";
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_ 1;
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};
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register CCR rw addr(base, 0xD14) "Configuration Control register"{
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_ 22;
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stkalign 1 "1 = align stack to 8 bytes before exception entry, 0 = align stack to 4 bytes";
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bfhfnmign 1 "all interrupt handlers with negative priority (NMI, hardfaults, escalated handlers) ignore all data bus faults";
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_ 3;
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div_0_trp 1 "trap on divide by 0. ";
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unalign_trp 1 "trap on unaligned access";
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_ 1;
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usersetmpend 1 "enable user code to write the Software Trigger Interrupt Register to pend a Main exception (associated with Main stack pointer)";
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nonbasethrdena 1 "0 = thread mode can only be entered when returning from last exception ,1 = thread mode can be entered from any level in Handler mode by controlled return value";
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};
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regarray SHPR addr(base, 0xD18) [3] "System Handler Priority Registers"
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type(priority_reg);
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register SHCSR rw addr(base, 0xD24) "System Handler Control and State register"{
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_ 13;
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usgfaultena 1 "enable usage faults";
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busfaultena 1 "enable bus faults";
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memfaultena 1 "enable memory manage interrupts";
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svcallpended 1 "reads 1 if SVcall pended";
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busfaultpended 1 "reads 1 if bus fault pended";
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memfaultpended 1 "reads 1 if memory manage pended";
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usgfaultpended 1 "reads 1 if usage fault pended";
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systickact 1 "reads 1 if SysTick is active";
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pendsvact 1 "reads 1 if pendSV is active";
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_ 1;
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monitoract 1 "reads 1 if monitor is active";
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svcallact 1 "reads 1 if SVcall is active";
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_ 3;
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usgfaultact 1 "reads 1 if usage fault is active";
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_ 1;
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busfaultact 1 "reads 1 if bus fault is active";
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memfaultact 1 "reads 1 if memory manage is active";
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};
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register CFSR rwc addr(base, 0xD28) "Configurable Fault Status register"{
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_ 6;
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divbyzero 1 "attempted division by 0 while div_by_zero enabled.";
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unaligned 1 "attempted unaligned access while unaligned_trp enabled";
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_ 4;
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nocp 1 "attempt to use a coprocessor instruction. processor does not support coprocessors";
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invpc 1 "attempt to load EXC_RETURN into PC illegaly. The return PC points to causing instruction";
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invstate 1 "invalid combination of EPSR and instruction, for reasons other than undefined instruction. The return PC points to causing instruction";
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undefinstr 1 "processor tried to execute undefined instruction. The return PC points to causing instruction";
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bfarvalid 1 "BFAR contains a valid address. ";
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_ 2;
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stkerr 1 "stacking from exception entry has caused bus fault. SP is still adjusted and pushed values might be incorrect. BFAR is not written";
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unstkerr 1 "unstack from exception return has caused bus fault. SP is not adjusted from failing return. BFAR is not written";
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impreciserr 1 "imprecise data bus error. BFAR is not written";
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preciserr 1 "precise data bus error";
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ibuserr 1 "instruction bus error. BFAR is not written.";
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mmarvalid 1 "MMAR contains a valid address. ";
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_ 2;
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mstkerr 1 "stacking from exception entry has caused access violations. SP is still adjusted and pushed values might be incorrect";
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munstkerr 1 "unstack from exception return has caused access violations. SP is not adjusted from failing return";
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_ 1;
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daccviol 1 "data access violation. loads MMAR with address of attemted access";
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iaccviol 1 "instruction access violation (such as trying to execute from a XN region). does not set MMAR";
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};
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register HFSR rwc addr(base, 0xD2C) "Hard Fault Status register"{
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debugevt 1 "debug related fault";
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forced 1 "configurable fault triggered but disabled or too low priority";
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_ 28;
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vecttbl 1 "bus fault while reading vector table";
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_ 1;
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};
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register DFSR rwc addr(base, 0xD30) "Debug Fault Status register"{
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_ 27;
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external 1 "external debug request flag";
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vcatch 1 "vector catch flag";
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dwttrap 1 "data watchpoint and trace flag";
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bkpt 1 "BKPT instruction executed";
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halted 1 "halt requested by NVIC";
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};
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register MMAR rw addr(base, 0xD34) "Memory Manage Fault Address register"{
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address 32 "address of a faulted load or store attempt";
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};
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register BFAR rw addr(base, 0xD38) "Bus Fault Address register"{
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address 32 "address of a faulted load or store attempt";
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};
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register AFSR rwc addr(base, 0xD3C) "Auxiliary Fault Status register"{
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impdef 32 "implementation defined. maps directly to AUXFAULT input signals";
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};
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register STIR wo addr(base, 0xF00) "Software Trigger Interrupt register"{
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_ 23;
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intid 9 "writing a value here is the same as manually pending an interrupt by setting the corresponding bit in the ISPR";
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};
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};
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