29 lines
781 B
Plaintext
29 lines
781 B
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_smpt.dev
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*
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* description: register definitions for the Xeon Phi system memory page tables
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*/
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device xeon_phi_smpt lsbfirst ( addr base ) "Intel Xeon Phi System Memory Page Tables" {
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: CSR_RESET, HOT_RESET
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* Register Access: TRM
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* Number: 32
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*/
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regarray entry rw addr(base, 3100) [32] "System Memory Page Table Entry" {
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value 32 "Value";
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};
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}; |