83 lines
2.0 KiB
ArmAsm
83 lines
2.0 KiB
ArmAsm
/* System initialisation shim
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This code is executed on boot, by the simulator, to initialise the hardware
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as the CPU driver expects it i.e. as initialised by UEFI/Hagfish.
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*/
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#define ASM_FILE
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#include <multiboot2.h>
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#define SHIM_STACK 256
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.global invalidate_caches, start
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/* We should begin in EL3, caches disabled. */
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start:
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/* A small stack to call into C. */
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adr x0, shim_stack
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add sp, x0, #(SHIM_STACK - 8)
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/* Invalidate the TLB */
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tlbi alle3
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/* Load the table base register, table must map this code 1-1. */
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ldr x0, p_kernel_table
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msr ttbr0_el3, x0
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/* Set memory attribute 0 to Normal, inner and outer WB, non-transient.
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* Set memory attribute 1 to Device, nGnRnE (strongly ordered). */
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mov x0, #0x00ff
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msr mair_el3, x0
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/* Set the translation paramaters. */
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mov x1, xzr
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mov x2, #5
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bfi x1, x2, #16, 3 /* 48b PA */
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/* orr x1, x1, #(0<<14) */ /* 4kB granule */
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orr x1, x1, #(3<<12) /* Table IS */
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orr x1, x1, #(1<<10) /* Table Outer WB, WA */
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orr x1, x1, #(1<< 8) /* Table Inner WB, WA */
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orr x1, x1, #16 /* 48b VA */
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msr tcr_el3, x1
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dsb sy
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/* Enable the MMU. */
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mrs x0, sctlr_el3
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orr x0, x0, #(1<<0) /* MMU control bit. */
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msr sctlr_el3, x0
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isb
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/* Enable Caches. */
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bl invalidate_caches
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dmb sy
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isb
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mrs x0, sctlr_el3
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orr x0, x0, #(1<<2) /* Cache control bit. */
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msr sctlr_el3, x0
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/* Switch to the kernel stack. */
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ldr x2, p_kernel_stack_top
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mov sp, x2
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/* Jump to the kernel entry point, passing the multiboot magic (boot
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* core), the address of the multiboot header, and the top of the kernel
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* stack. */
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ldr x0, magic
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ldr x1, p_multiboot
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ldr x5, p_entry
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br x5
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/* These pointers are filled in at load time. */
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.align 8
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p_entry: .dword 0
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p_multiboot: .dword 0
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p_kernel_table: .dword 0
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p_kernel_stack_top: .dword 0
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magic:
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.word MULTIBOOT2_BOOTLOADER_MAGIC
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.align 8
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shim_stack:
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.space SHIM_STACK
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