480 lines
21 KiB
Plaintext
480 lines
21 KiB
Plaintext
/*
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* Copyright (c) 2019, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* enet.dev
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*
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* DESCRIPTION: imx8x network device
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*
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* Number refer to i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual
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*/
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device enet lsbfirst ( addr base ) "Imx8x enet controller" {
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/****************************************************************************
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* 14.6.5.1/3630 Interrupt Event Register
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***************************************************************************/
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register eir rw addr(base, 0x0004) "Interrupt Event Register" {
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rxb1 1 rw1c "Receive buffer interrupt class 1";
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rxf1 1 rw1c "Receive frame interrupt class 1";
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txb1 1 rw1c "Transmit buffer interrupt class 1";
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txf1 1 rw1c "Transmit frame interrupt class 1";
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rxb2 1 rw1c "Receive buffer interrupt class 2";
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rxf2 1 rw1c "Receive frame interrupt class 2";
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txb2 1 rw1c "Transmit buffer interrupt class 2";
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txf2 1 rw1c "Transmit frame interrupt class 2";
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_ 1 rsvd;
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parsrf 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRF].";
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parsrr 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRR].";
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_ 1 rsvd;
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rxflush0 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_0]";
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rxflush1 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_1]";
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rxflush2 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_2]";
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ts_timer 1 rw1c "TS_TIMER interrupt mask";
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ts_avail 1 rw1c "TS_AVAIL interrupt mask";
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wakeup 1 rw1c "WAKEUP interrupt mask";
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plr 1 rw1c "PLR interrupt mask";
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un 1 rw1c "UN interrupt mask";
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rl 1 rw1c "RL interrupt mask";
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lc 1 rw1c "LC interrupt mask";
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eberr 1 rw1c "EBERR interrupt mask";
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mii 1 rw1c "MII interrupt mask";
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rxb 1 rw1c "RXB interrupt mask";
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rxf 1 rw1c "RXF interrupt mask";
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txb 1 rw1c "TXB interrupt mask";
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txf 1 rw1c "TXF interrupt mask";
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gra 1 rw1c "GRA interrupt mask";
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babt 1 rw1c "BABT interrupt mask";
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babr 1 rw1c "BABR interrupt mask";
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_ 1 rsvd;
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};
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/****************************************************************************
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* 14.6.5.2/3634 Interrupt Mask Register
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***************************************************************************/
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register eimr rw addr(base, 0x0008) "Interrupt Mask Register" {
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rxb1 1 "Receive buffer interrupt class 1";
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rxf1 1 "Receive frame interrupt class 1";
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txb1 1 "Transmit buffer interrupt class 1";
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txf1 1 "Transmit frame interrupt class 1";
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rxb2 1 "Receive buffer interrupt class 2";
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rxf2 1 "Receive frame interrupt class 2";
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txb2 1 "Transmit buffer interrupt class 2";
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txf2 1 "Transmit frame interrupt class 2";
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_ 1 rsvd;
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parsrf 1 "Interrupt mask bit corresponding to EIR[PARSRF].";
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parsrr 1 "Interrupt mask bit corresponding to EIR[PARSRR].";
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_ 1 rsvd;
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rxflush0 1 "Corresponds to interrupt source EIR[RXFLUSH_0]";
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rxflush1 1 "Corresponds to interrupt source EIR[RXFLUSH_1]";
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rxflush2 1 "Corresponds to interrupt source EIR[RXFLUSH_2]";
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ts_timer 1 "TS_TIMER interrupt mask";
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ts_avail 1 "TS_AVAIL interrupt mask";
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wakeup 1 "WAKEUP interrupt mask";
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plr 1 "PLR interrupt mask";
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un 1 "UN interrupt mask";
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rl 1 "RL interrupt mask";
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lc 1 "LC interrupt mask";
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eberr 1 "EBERR interrupt mask";
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mii 1 "MII interrupt mask";
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rxb 1 "RXB interrupt mask";
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rxf 1 "RXF interrupt mask";
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txb 1 "TXB interrupt mask";
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txf 1 "TXF interrupt mask";
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gra 1 "GRA interrupt mask";
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babt 1 "BABT interrupt mask";
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babr 1 "BABR interrupt mask";
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_ 1 rsvd;
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};
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/****************************************************************************
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* 14.6.5.3/3638
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***************************************************************************/
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register rdar rw addr(base, 0x0010) "Receive Descriptor Active Register ring0" {
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_ 24 rsvd;
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rdar 1 "Receive Descriptor Active";
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_ 7 rsvd;
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};
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/****************************************************************************
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* 14.6.5.3/3638
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***************************************************************************/
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register tdar rw addr(base, 0x0014) "Transmit Descriptor Active Register ring0" {
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_ 24 rsvd;
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tdar 1 "Transmit Descriptor Active";
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_ 7 rsvd;
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};
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/****************************************************************************
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* 14.6.5.5/3640 Ethernet control register
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***************************************************************************/
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register ecr rw addr(base, 0x0024) "Control register" {
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reset 1 "Ethernet MAC Reset";
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etheren 1 "Ethernet enable";
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magicen 1 "Magic packet detection enable";
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sleep 1 "Sleep Mode enable";
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en1588 1 "EN1588 Enable";
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speed 1 "Select between 10/100 Mbit (0) and 1000 Mbit (1)";
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dbgen 1 "Debug enable";
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_ 1 rsvd;
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dbswp 1 "Descriptor Byte Swapping Enable";
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svlanen 1 "S-VLAN enable";
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vlanuse2nd 1 "VLAN use second tag";
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svlandbl 1 "S-VLAN double tag";
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_ 4 rsvd;
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txc_dly 1 "Transmit clock delay";
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rxc_dly 1 "Receive clock delay";
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_ 14 rsvd;
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};
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/****************************************************************************
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* 14.6.5.6/3643 MII Management Frame Register
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***************************************************************************/
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register mmfr rw addr(base, 0x0040) "MII Management Frame Register" {
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data 16 "Data written to or read from PHY register";
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ta 2 "Turn Around: needs to be programmed to 10 to be valid";
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ra 5 "Register Address";
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pa 5 "Phy address";
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op 2 "Operation Code";
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st 2 "Start of Frame Delimeter";
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};
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/****************************************************************************
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* 14.6.5.6/3643 MII Speed Control Register
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***************************************************************************/
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register mscr rw addr(base, 0x0044) "MII Speed Control Register" {
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_ 1 rsvd;
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mii_speed 6 "MII Speed";
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dis_pre 1 "Disable preamble";
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hold_time 3 "Hold time on MDIO Output";
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_ 21 rsvd;
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};
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/****************************************************************************
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* 14.6.5.9/3646 Receive Control Register
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***************************************************************************/
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register rcr rw addr(base, 0x0084) "Receive Control Register" {
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loop 1 "Internal Loopback";
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drt 1 "Disable Receive on Transmit";
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mii_mode 1 "Media Independant Interface Mode";
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prom 1 "Promiscuous Mode";
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bc_rej 1 "Broadcast Frame Reject";
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fce 1 "Flow Control Enable";
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rgmii_en 1 "RGMII Mode Enable";
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_ 1 rsvd;
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rmii_mode 1 "RMII Mode Enable";
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rmii_10t 1 "Enable 10-Mbits/mode of the RMII or RGMII";
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_ 2 rsvd;
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paden 1 "Enable Frame Padding Remove On Receive";
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paufwd 1 "Terminate/Forward Pause Frames";
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crcfwd 1 "Terminate/Forward Receive CRC";
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cfen 1 "MAC Control Frame Enable";
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max_fl 14 "Maximum Frame Length";
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nlc 1 "Payload Length Check Disable";
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grs 1 "Graceful Receive Stop";
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};
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/****************************************************************************
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* 14.6.5.11/3649 Transmit Control Register
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***************************************************************************/
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// 14.6.5.10
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register tcr rw addr(base, 0x000C4) "Transmit Control Register" {
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gts 1 "Graceful Transmit Stop";
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_ 1 rsvd;
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fden 1 "Full-Duplex Enable";
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tfc_pause 1 "Transmit Frame Control Pause";
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rfc_pause 1 "Receive Frame Control Pause";
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addsel 3 "Source MAC Address Select on Transmit";
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addins 1 "Set MAC Address on Transmit";
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crcfwd 1 "Forward Frame From Application With CRC";
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_ 1 rsvd;
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_ 21 rsvd;
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};
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/****************************************************************************
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* 14.6.5.11/3651 Physical Address Lower Register
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***************************************************************************/
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// 14.6.5.11
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register palr rw addr(base, 0x000E4) "Physical Address Lower Register" {
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paddr1 32 "Pause Address";
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};
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/****************************************************************************
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* 14.6.5.12/3651 Physical Address Upper Register
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***************************************************************************/
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register paur rw addr(base, 0x000E8) "Physical Address Upper Register" {
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typ 16 "Always contains 0x8808";
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paddr2 16 "Pause Address";
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};
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/****************************************************************************
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* 14.6.5.12/3651 Opcode/Pause Duration Register
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***************************************************************************/
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register opd rw addr(base, 0x000EC) "Opcode/Pause Duration Register" {
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pause_dur 16 "Pause duration";
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opcode 16 "Opcode Field in Pause Frames";
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};
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/****************************************************************************
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* 14.6.5.16/3654 Descriptor Individual Upper Address
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***************************************************************************/
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register iaur rw addr(base, 0x00118) "Descriptor Individual Upper Address Reg" {
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iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion";
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};
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/****************************************************************************
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* 14.6.5.17/3655 Descriptor Individual Lower Address
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***************************************************************************/
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register ialr rw addr(base, 0x0011C) "Descriptor Individual Lower Address Reg" {
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iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion";
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};
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/****************************************************************************
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* 14.6.5.18/3656 Descriptor Group Upper Address
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***************************************************************************/
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register gaur rw addr(base, 0x00120) "Descriptor Individual Upper Address Reg" {
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iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion";
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};
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/****************************************************************************
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* 14.6.5.19/3656 Descriptor Group Lower Address
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***************************************************************************/
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register galr rw addr(base, 0x00124) "Descriptor Individual Lower Address Reg" {
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iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion";
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};
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/****************************************************************************
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* 14.6.5.20/3657 Transmit FIFO Watermark Register
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***************************************************************************/
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register tfwr rw addr(base, 0x00144) "Transmit FIFO Watermark Register " {
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tfwr 6 "Transmit FIFO Write";
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_ 2 rsvd;
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strfwd 1 "Store and Forward Enable";
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_ 23 rsvd;
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};
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/****************************************************************************
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* 14.6.5.27/3662 Receive Descriptor Ring 0 Start Register
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***************************************************************************/
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register rdsr rw addr(base, 0x00180) "Receive Descriptor Ring 0 Start Register" {
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_ 3 rsvd;
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start 29 "Pointer to the beginning of receive descriptor queue";
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};
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/****************************************************************************
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* 14.6.5.28/3663 Transmit Descriptor Ring 0 Start Register
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***************************************************************************/
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register tdsr rw addr(base, 0x00184) "Transmit Descriptor Ring 0 Start Register" {
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_ 3 rsvd;
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start 29 "Pointer to the beginning of transmit descriptor queue";
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};
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/****************************************************************************
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* 14.6.5.29/3663 Maximum Receive Buffer Size Register ring 0
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***************************************************************************/
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register mrbr rw addr(base, 0x00188) "Receive Descriptor Ring 0 Start Register" {
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_ 4 rsvd;
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start 10 "Receive buffer size in bytes";
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_ 18 rsvd;
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};
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/****************************************************************************
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* 14.6.5.30/3664 Receive FIFO Section Full Threshold
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***************************************************************************/
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register rsfl rw addr(base, 0x00190) "Receive FIFO Section Full Threshold" {
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rx_section_full 10 "Value of Receive FIFO Sectoin Full Threshold";
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_ 22 rsvd;
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};
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/****************************************************************************
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* 14.6.5.31/3665 Receive FIFO Section Empty Threshold
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***************************************************************************/
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register rsem rw addr(base, 0x00194) "Receive FIFO Section Empty Threshold" {
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rx_section_empty 10 "Value of Receive FIFO Sectoin Empty Threshold";
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_ 6 rsvd;
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stat_section_empty 5 "RX Status Section Empty Threshold";
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_ 11 rsvd;
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};
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/****************************************************************************
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* 14.6.5.32/3665 Receive FIFO Almost Empty Threshold
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***************************************************************************/
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register raem rw addr(base, 0x00198) "Receive FIFO Almost Empty Threshold" {
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rx_almost_full 10 "Value of Receive FIFO Almost Empty Threshold";
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_ 22 rsvd;
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};
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/****************************************************************************
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* 14.6.5.33/3666 Receive FIFO Almost Empty Threshold
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***************************************************************************/
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register rafl rw addr(base, 0x0019C) "Receive FIFO Almost Full Threshold" {
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rx_almost_empty 10 "Value of Receive FIFO Almost Full Threshold";
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_ 22 rsvd;
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};
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/****************************************************************************
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* 14.6.5.40/3745
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***************************************************************************/
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register racc rw addr(base, 0x001C4) "Receive Accelerator Function Configuration" {
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padrem 1 "";
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ipdis 1 "";
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prodis 1 "";
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_ 3 rsvd;
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linedis 1 "Enable Discard Of Frames With MAC Layer Errors";
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shift16 1 "";
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_ 24 rsvd;
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};
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/****************************************************************************
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* 14.6.5.49/3679 Tx Packet Count Statistic Register
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***************************************************************************/
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register rmon_t_packets rw addr(base, 0x00204) "Tx Packet Count Statistic Register" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.50/3680 Tx Broadcast Packet Count Statistic Register
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***************************************************************************/
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register rmon_t_bc_pkt rw addr(base, 0x00208) "Tx Broadcast Packet Count Statistic Register" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.51/3680 Tx Multicast Packet Count Statistic Register
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***************************************************************************/
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register rmon_t_mc_pkt rw addr(base, 0x0020C) "Tx Multicast Packet Count Statistic Register" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.52/3681 Tx Packets with CRC/Align Error Statistic Register
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***************************************************************************/
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register rmon_t_crc_align rw addr(base, 0x00210) "Tx Packets with CRC/Align Error Statistic Register" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.53/3681 Tx Packets Less Than Bytes and Good CRC Statistics
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***************************************************************************/
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register rmon_t_undersize rw addr(base, 0x00214) "Tx Packets Less Than Bytes and Good CRC Statistics" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.54/3681 Tx Packets GT MAX_FL bytes and Good CRC Statistics
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***************************************************************************/
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register rmon_t_oversize rw addr(base, 0x00218) "Tx Packets GT MAX_FL bytes and Good CRC Statistics" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.55/3681 Tx Packets Less Than Bytes and bad CRC Statistics
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***************************************************************************/
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register rmon_t_frag rw addr(base, 0x0021C) "Tx Packets Less Than Bytes and bad CRC Statistics" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.54/3682 Tx Packets GT MAX_FL bytes and bad CRC Statistics
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***************************************************************************/
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register rmon_t_jab rw addr(base, 0x00220) "Tx Packets GT MAX_FL bytes and bad CRC Statistics" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.55/3683 Tx Collision Count Statistic Register
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***************************************************************************/
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register rmon_t_col rw addr(base, 0x00224) "Tx Collision Count Statistic Register" {
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count 16 "Number of packets sent";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.79/3766 Rx Packet Count Statistic Register
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***************************************************************************/
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register rmon_r_packets rw addr(base, 0x00284) "Rx Packet Count Statistic Register" {
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count 16 "Number of packets received";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.81/3767 Rx Packets with CRC/Align Error Statistic Register
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***************************************************************************/
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register rmon_r_packets_crc_align rw addr(base, 0x00290) "Rx Packets with CRC/Align Error Statistic Register" {
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count 16 "Number of packets received with CRC or align error";
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_ 16 rsvd;
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};
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/****************************************************************************
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* 14.6.5.94/3767 Rx Octets Statistic Register
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***************************************************************************/
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register rmon_r_octets rw addr(base, 0x002C4) "Rx Packets with CRC/Align Error Statistic Register" {
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count 32 "Number of received octets";
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};
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/****************************************************************************
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* 14.6.5.95/3773 Frame not Counted Correctly Statistic Register
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***************************************************************************/
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register iee_r_drop rw addr(base, 0x002C8) "Frame not Counted Correctly Statistic Register" {
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count 16 "Frame count";
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_ 16 rsvd;
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};
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datatype bufdesc "Legacy descriptor" {
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len 16 "Data length";
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sc 16 "Control and status info";
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addr 32 "Buffer address";
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};
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/*
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datatype bufdesc_ex "Enhanced descriptor" {
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sc 16 "Control and status info";
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len 16 "Data length";
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addr 32 "Buffer address";
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esc 32 "";
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prot 32 "";
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ts 32 "";
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res0 64 "";
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};
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*/
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};
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