185 lines
8.1 KiB
Plaintext
185 lines
8.1 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_boot.dev
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*
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* description: register definitions for the Xeon Phi Boot Time Registers
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*/
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device xeon_phi_boot lsbfirst ( addr sbox_base, addr dbox_base ) "Intel Xeon Phi Boot Registers" {
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: CSR_RESET, HOT_RESET
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* Register Access: TRM
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*/
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register flash_ctrl rw addr(sbox_base, 0xAB24) {
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percent 7 "Percentage progress";
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status 4 "Status code";
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command 4 "flash command";
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smc_status 4 "SMC Status";
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_ 5 "Reserved";
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cmd_data 7 "Command Data";
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mm_debug 1 "Memory debug";
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};
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constants offset width(32) "" {
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address_shift=12;
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address_mask=0xfffff000;
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};
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/*
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* alias for scratch register 2
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*/
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register download rw addr(sbox_base, 0xAB28) {
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status 1 "Download status bit";
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apicid 9 "APIC ID to send the boot interrupt";
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_ 2 "unused";
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offset 20 "Load offset";
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};
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/*
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* alias for scratch register 3
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*/
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register res_size rw addr(sbox_base, 0xAB2C) {
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os 32 "Reserved size";
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};
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/*
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* alias for scratch register 5
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*/
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register os_size rw addr(sbox_base, 0xAB34) {
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size 32 "Size of the loaded image";
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};
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constants mem width(2) "" {
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mem_all = 0x0;
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mem_half = 0x1;
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mem_third = 0x2;
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mem_fourth = 0x3;
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};
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register meminfo rw addr(sbox_base, 0xAB20) {
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test_disable 1 "Memtest disable";
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usage 2 "Memory usage";
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size_kb 29 "Memory size in KB";
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};
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register reset rw addr(sbox_base, 0x4010) {
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reset 1 "Perform device rest";
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_ 31;
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};
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/*
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* Note: The post codes are represented as a two byte ASCII values
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*/
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constants postcodes width(16) "The Xeon Phi Post codes" {
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postcode_lidt = 0x3130 "01 LIDT";
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postcode_sboxinit = 0x3230 "02 SBOX initialization";
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postcode_gddrtop = 0x3330 "03 Set GDDR Top";
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postcode_memtest = 0x3430 "04 Begin memory test";
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postcode_e820 = 0x3530 "05 Program E820 table";
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postcode_dbox = 0x3630 "06 Initialize DBOX";
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postcode_cache = 0x3930 "09 Enable Cache";
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postcode_initap = 0x6230 "0b Pass initialization params to APs";
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postcode_code = 0x6330 "0c Cache C code";
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postcode_mp = 0x4530 "0E Program MP table";
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postcode_apwkup = 0x4630 "0F Wake up APs";
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postcode_apboot = 0x3031 "10 Wait for APs to boot";
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postcode_sig = 0x3131 "11 Signal host to download OS";
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postcode_ready = 0x3231 "12 Wait for download READY";
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postcode_boot = 0x3331 "13 Signal to boot received";
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postcode_pinfo = 0x3531 "15 Report platform information";
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postcode_ptable = 0x3731 "17 Page table setup";
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postcode_memtrain = 0x3033 "30 Begin memory training";
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postcode_gddrtrain = 0x3133 "31 GDDR Training to query memory modules";
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postcode_findgddrtrain = 0x3233 "32 Find GDDR training parameters in flash";
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postcode_mmiotrain = 0x3333 "33 MMIO training";
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postcode_rcomptrain = 0x3433 "34 RCOMP training";
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postcode_dcctrain = 0x3533 "35 DCC disable training";
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postcode_hcktrain = 0x3633 "36 HCK training";
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postcode_ucodetrain = 0x3733 "37 UCode Training";
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postcode_vendortrain = 0x3833 "38 Vendor specific training";
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postcode_addrtrain = 0x3933 "39 GDDR address training";
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postcode_gddrident = 0x4133 "3A GDDR memory module identification";
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postcode_wcktrain = 0x6233 "3b GDDR WCK training";
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postcode_cdrdtrain = 0x4333 "3C GDDR read training with CDR enabled";
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postcode_cdretrain = 0x6433 "3d GDDR Read Training with CDR disabled";
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postcode_wrtrain = 0x4533 "3E GDDR Write Training";
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postcode_fintrain = 0x4633 "3F Finalize GDDR Training";
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postcode_osauth = 0x3034 "40 Begin Coprocessor OS authentification";
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postcode_loading0 = 0x3035 "50 Coprocessor OS Loading 0";
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postcode_loading1 = 0x3135 "51 Coprocessor OS Loading 1";
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postcode_loading2 = 0x3235 "52 Coprocessor OS Loading 2";
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postcode_loading3 = 0x3335 "53 Coprocessor OS Loading 3";
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postcode_loading4 = 0x3435 "54 Coprocessor OS Loading 4";
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postcode_loading5 = 0x3535 "55 Coprocessor OS Loading 5";
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postcode_loading6 = 0x3635 "56 Coprocessor OS Loading 6";
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postcode_loading7 = 0x3735 "57 Coprocessor OS Loading 7";
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postcode_loading8 = 0x3835 "58 Coprocessor OS Loading 8";
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postcode_loading9 = 0x3935 "59 Coprocessor OS Loading 9";
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postcode_loadingb = 0x4135 "5A Coprocessor OS Loading A";
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postcode_loadinga = 0x4235 "5B Coprocessor OS Loading B";
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postcode_loadingc = 0x4335 "5C Coprocessor OS Loading C";
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postcode_loadingd = 0x4435 "5D Coprocessor OS Loading D";
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postcode_loadinge = 0x4535 "5E Coprocessor OS Loading E";
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postcode_loadingf = 0x4635 "5F Coprocessor OS Loading F";
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postcode_gp = 0x5036 "6P Int 13 - General Protection Fault";
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postcode_tss = 0x3537 "75 Int 10 - Invalid TSS";
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postcode_fpu = 0x3738 "87 Int 16 - x87 FPU Error";
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postcode_algin = 0x4341 "AC INT 17 - Alignment Check";
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postcode_bp = 0x5062 "bP INT 3 - Break Point";
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postcode_bound = 0x7262 "br INT 5 - BOUND Range Exceeded";
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postcode_mc = 0x4343 "CC INT 18 - Machine Check";
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postcode_seg = 0x6F63 "co INT 9 - Coprocessor Segmenet Overrun";
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postcode_dbg = 0x6264 "db INT 1 - Debug";
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postcode_div = 0x4564 "dE INT 0 - Divide Error";
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postcode_df = 0x4664 "dF INT 8 - Double Fault";
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postcode_memf = 0x4545 "EE Memory Test Failed";
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postcode_pnf = 0x3046 "F0 GDDR Parameters not found";
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postcode_pllf = 0x3146 "F1 GBOX PLL lock failure";
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postcode_memtf = 0x3246 "F2 GDDR failed memory training";
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postcode_memqf = 0x3346 "F3 GDDR memory module query failed";
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postcode_mempf = 0x3446 "F4 Memory preservation failure";
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postcode_sf = 0x3546 "F5 INT 12 - Stack Fault";
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postcode_done = 0x4646 "FF - Bootstrap finished execution";
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postcode_ld = 0x644C "Ld - Locking down hardware access";
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postcode_authf = 0x416E "nA - OS Image failed Authentification";
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postcode_dna = 0x646E "nd INT 7 - Device not Available";
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postcode_nmi = 0x6F6E "no INT 2 - Non-maskable Interrupt";
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postcode_snp = 0x506E "nP INT 11 - Segment Not Present";
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postcode_of = 0x466F "oF INT 4 - Overflow";
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postcode_pf = 0x4650 "PF INT 14 - Pagefault";
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postcode_rs = 0x3572 "r5 INT 15 - Reserved";
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postcode_iop = 0x6475 "ud INT 6 - Invalid OP code";
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postcode_unknownerr = 0x3048 "H0 Unknown Error, HALT";
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};
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constants postcodes_special width(32) "The Xeon Phi Post codes" {
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postcode_invalid = 0x0;
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postcode_fatal = 0xffffffff;
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};
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register postcode rw addr(dbox_base, 0x242c) {
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code 16 type(postcodes);
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_ 16;
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};
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register postcode_raw rw also addr(dbox_base, 0x242c) {
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code0 8;
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code1 8;
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_ 16;
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};
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};
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