62 lines
2.8 KiB
Plaintext
62 lines
2.8 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_dct_l3interconnect.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_dct_l3interconnect msbfirst ( addr base ) "" {
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register dct_version ro addr(base, 0x0) "IP Revision" type(uint32);
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register dct_ctrl addr(base, 0x4) "DCT control register" {
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_ 16 mbz;
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busy 1 ro "IDCT/busy status 0: Idle 1: Busy";
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_ 14 mbz;
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en 1 wo "Write 1 whenDCT_CFG[4] TRIG_SRC = 0 to start module operation. Read returns 0.";
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};
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register dct_cfg addr(base, 0x8) "DCT configuration register" {
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_ 18 mbz;
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nmcus 6 rw "Number of MCUs (for FMT = 0, 1) or blocks (for FMT = 2) 0 = 1 MCU or block 1 = 2 MCUs or blocks ... 63 = 64 MCUs or blocks";
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_ 2 mbz;
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autogating 1 rw "Internal clock gating on interface and functional clocks 0: Clocks are free-running 1: Clocks are gated off in subblocks that are not required for operation.";
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trig_src 1 rw "Trigger source 0: Memory mapper register 1: Hardware start signal";
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inten 1 rw "0: Interrupt disabled 1: Interrupt enabled";
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fmt 2 rw "Data format 0: YUV4:2:0 format 1: YUV4:2:2 format 2: Sequential blocks format 3: Reserved";
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mode 1 rw "0: DCT 1: IDCT";
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};
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register dct_sptr addr(base, 0xC) "Spatial-domain data pointer, byte address" {
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_ 19 mbz;
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addr 8 rw "Address in 256-bit words Intention is that software write a byte address into the register. Hardware ignores the lowest 5 bits and bits 12..5 specifies the 256-bit/word memory address..";
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_ 5 mbz;
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};
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register dct_fptr addr(base, 0x10) "Frequency-domain data pointer, byte address" {
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_ 18 mbz;
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addr 10 rw "Address in 128-bit words. Intention is that software write a byte address into the register. Hardware ignores the lowest 4 bits and bits 13..4 specifies the 128-bit/word memory address.";
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_ 4 mbz;
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};
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}; |