69 lines
1.4 KiB
C
69 lines
1.4 KiB
C
/**
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* \file
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* \brief Some arch specific asm inlines
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*/
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/*
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* Copyright (c) 2015, ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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#ifndef ARCH_AARCH64_BARRELFISH_KPI_ASM_INLINES_H
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#define ARCH_AARCH64_BARRELFISH_KPI_ASM_INLINES_H
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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static inline uint64_t rdtsc(void)
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{
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uint64_t ccnt = 0;
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__asm__ volatile("mrs %[ccnt], CNTPCT_EL0;" : [ccnt] "=r" (ccnt));
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return ccnt;
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}
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static inline uint64_t rdtscp(void)
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{
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uint64_t ccnt;
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/* An ISB flushes the pipeline, and re-fetches the instructions from the
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* cache or memory and ensures that the effects of any completed
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* context-changing operation before the ISB are visible to any instruction
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* after the ISB
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*/
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__asm__ volatile("isb" : : : "memory");
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__asm__ volatile("mrs %[ccnt], CNTVCT_EL0;" : [ccnt] "=r" (ccnt));
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return ccnt;
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}
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static inline void dmb(void)
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{
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__asm volatile ("dmb sy" : : : "memory");
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}
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static inline uint8_t is_cycle_counter_overflow(void)
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{
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//NYI
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return 0;
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}
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static inline uint32_t get_cycle_count(void)
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{
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//NYI
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return 0;
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}
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static inline void reset_cycle_counter(void)
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{
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//NYI
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}
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#endif // __ASSEMBLER__
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#endif // ARCH_AARCH64_BARRELFISH_KPI_ASM_INLINES_H
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