268 lines
7.1 KiB
Plaintext
268 lines
7.1 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xapic.dev
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*
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* DESCRIPTION: Local eXtended APIC hardware description
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*
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* Numbers in comments refer to the Intel Software Development Manual
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* volume 3, October 2007.
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*/
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device xapic lsbfirst ( addr base ) "Local APIC" {
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// 8.4.6
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register id rw addr(base, 0x0020) "Local APIC ID" {
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_ 24;
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id 8 "apic id";
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};
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/*
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* the xeon phi has a slighly different register layout than normal xapic
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*/
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register id_xeon_phi rw also addr(base, 0x0020) "Local APIC ID (Xeon Phi)" {
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_ 23;
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id 9 "apic id";
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};
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// 8.4.8
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register version ro addr(base, 0x0030) "Local APIC Version" {
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ver 8 "version";
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_ 8;
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max_lvt 8 "max LVT entry";
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_ 8;
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};
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// 8.5.1
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constants timer_mode "Timer mode" {
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one_shot = 0;
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periodic = 1;
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tsc_deadline = 2;
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};
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constants int_mask "Interrupt mask" {
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not_masked = 0 "Not masked";
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masked = 1 "Masked";
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};
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register lvt_timer rw addr(base, 0x0320) "LVT Timer" {
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vector 8 "Vector";
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_ 4;
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status 1 "Delivery status";
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_ 3;
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mask 1 type(int_mask) "Masked";
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mode 2 type(timer_mode) "Mode";
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_ 13;
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};
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constants vdm "Vector delivery mode" {
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fixed = 0b000 "Fixed";
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lowest = 0b001 "Lowest priority";
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smi = 0b010 "SMI";
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nmi = 0b100 "NMI";
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init = 0b101 "INIT";
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startup = 0b110 "Start Up";
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extint = 0b111 "ExtINT";
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};
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constants trigm "Trigger mode" {
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edge = 0 "Edge";
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level = 1 "Level";
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};
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regtype lvt_lint "LVT Int" {
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vector 8 "Vector";
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dlv_mode 4 type(vdm) "Delivery mode";
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_ 1;
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status 1 "Delivery status";
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pinpol 1 "Pin polarity";
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rirr 1 "Remote IRR";
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trig_mode 1 type(trigm) "Trigger mode";
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mask 1 type(int_mask) "Mask";
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_ 14;
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};
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register lvt_lint0 rw addr(base, 0x0350) type (lvt_lint);
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register lvt_lint1 rw addr(base, 0x0360) type (lvt_lint);
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register lvt_err rw addr(base, 0x0370) {
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vector 8 "Vector";
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_ 4;
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status 1 "Delivery status";
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_ 3;
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mask 1 type(int_mask) "Mask";
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_ 15;
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};
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regtype lvt_mon "LVT monitor" {
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vector 8 "Vector";
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msgType 3;
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_ 1;
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status 1 "Delivery status";
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_ 3;
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mask 1 type(int_mask) "Masked";
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_ 15;
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};
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register lvt_perf_cnt rw addr(base, 0x0340) type (lvt_mon);
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register lvt_thermal rw addr(base, 0x0330) type (lvt_mon);
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// 8.5.3
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register esr rw addr(base, 0x0280) "Error Status" {
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sce 1 "Send checksum error";
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rce 1 "Receive checksum error";
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sae 1 "Send accept error";
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rae 1 "Receive accept error";
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_ 1;
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siv 1 "Send illegal vector";
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riv 1 "Receive illegal vector";
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ira 1 "Illegal register address";
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_ 24;
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};
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// 8.5.4
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constants divide "Timer Divide values" {
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by1 = 0b1011;
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by2 = 0b0000;
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by4 = 0b0001;
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by8 = 0b0010;
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by16 = 0b0011;
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by32 = 0b1000;
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by64 = 0b1001;
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by128 = 0b1010;
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};
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register dcr rw addr(base, 0x03e0) "Divide Configuration" {
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div_val 4 "Timer divide value";
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_ 28;
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};
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register init_count rw addr(base, 0x0380) "Initial Count" type(uint32);
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register cur_count rw addr(base, 0x0390) "Current Count" type(uint32) ;
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// 8.6.1
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constants dst_shorthand "Destination shorthand" {
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none = 0b00 "No shorthand";
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self = 0b01 "Self";
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all_inc = 0b10 "All including self";
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all_exc = 0b11 "All excluding self";
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};
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constants dst_mode "Destination mode" {
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dst_phys = 0b00 "Physical";
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dst_log = 0b01 "Logical";
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};
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constants int_level "Interrupt level" {
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lvl_clr = 0b00 "Clear";
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lvl_set = 0b01 "Set";
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};
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register icr_lo rw addr(base, 0x0300) "Interrupt Command (lo)" {
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vector 8 "Vector";
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dlv_mode 3 type(vdm) "Delivery mode";
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dst_mode 1 type(dst_mode) "Destination mode";
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dlv_stat 1 ro "Delivery status";
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_ 1;
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level 1 type(int_level) "Level";
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trig_mode 1 type(trigm) "Trigger mode";
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_ 2;
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dst_short 2 type(dst_shorthand) "Destination shorthand";
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_ 12;
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};
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register icr_hi rw addr(base, 0x0310) "Interrupt Commmand (hi)" {
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_ 24;
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dest 8 "Destination field";
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};
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/*
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* the xeon phi has a slightly different register layout than normal apic
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*/
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register icr_hi_xeon_phi rw also addr(base, 0x0310) "Interrupt Commmand (hi)" {
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_ 16;
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dest 16 "Destination field";
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};
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// 8.6.2
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register ldr rw addr(base, 0x00d0) "Logical Destination" {
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_ 24;
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log_id 8 "Logical APIC ID";
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};
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register ldr_xeon_phi rw also addr(base, 0x00d0) "Logical Destination" {
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_ 16;
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log_id 16 "Logical APIC ID";
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};
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constants model_type "Destination model type" {
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flat = 0b1111;
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cluster = 0b0000;
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};
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register dfr rw addr(base, 0x00e0) "Destination Format" {
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_ 28 mb1;
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model 4 type(model_type) "Model";
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};
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regtype priority "Various priorities" {
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sub_class 4 "Priority subclass";
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priority 4 "Priority";
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_ 24;
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};
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register apr ro addr(base, 0x0090) "Arbitration priority" type(priority);
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// 8.8.3
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register tpr rw addr(base, 0x0080) "Task priority" type(priority);
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register ppr ro addr(base, 0x00A0) "Processor priority" type(priority);
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// 8.8.4
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regarray isr ro addr(base, 0x0100) [8; 0x10] "ISR" type(uint32);
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regarray tmr ro addr(base, 0x0180) [8; 0x10] "TMR" type(uint32);
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regarray irr ro addr(base, 0x0200) [8; 0x10] "IRR" type(uint32);
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// 8.8.5
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register eoi wo addr(base, 0x00b0) "End Of Interrupt" type(uint32);
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// 8.9
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register svr rw addr(base, 0x00f0) "Spurious Interrupt Vector Register" {
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vector 8 "Vector";
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enable 1 "APIC Software Enable/Disable";
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focus 1 "Focus Processor Checking";
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_ 22;
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};
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/*
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* AMD extensions: see AMD64 Architecture Programmer's Manual,
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* vol. 2 rev 3.14 (September 2007).
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*/
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// 16.7.1
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register eafr ro addr(base, 0x0400) "Extended APIC feature" {
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inc 1 "Interrupt enable register capable";
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snic 1 "Specific EOI capable";
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xaidc 1 "Extended APIC ID capability";
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_ 13 mbz;
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xlc 8 "Extended LVT count";
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_ 8 mbz;
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};
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// 16.3.5
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register eacr addr(base, 0x0410) "Extended APIC control" {
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iern 1 "Enable interrupt enable registers";
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sn 1 "Enable SEOI generation";
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xaidn 1 "Extended APIC ID enable";
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_ 29;
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};
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// 16.7.2
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register seoi wo addr(base, 0x0420) "Specific end-of-interrupt" {
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vector 8 "Vector";
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_ 24 mbz;
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};
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// 16.7.3
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regarray ier ro addr(base, 0x0480) [8; 0x10] "IER" type(uint32);
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};
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