455 lines
17 KiB
Plaintext
455 lines
17 KiB
Plaintext
/*
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* Copyright (c) 2014, University of Washington.
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* Copyright (c) 2018, ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich.
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* Attn: Systems Group.
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*/
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device vtd msbfirst ( addr base, addr iotlb, addr frr) "VT-d" {
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//////////////////////////// Translation Structure Formats ////////////////////////////
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datatype root_entry "Root Entry" {
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_ 64 mbz;
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ctp 52 "Context-table Pointer";
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_ 11 mbz;
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p 1 "Present";
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};
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datatype ext_root_entry "Extended Root Entry" {
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uctp 52 "Upper Context-table Pointer";
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_ 11 mbz;
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up 1 "Upper present";
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lcpt 52 "Lower Context-table Pointer";
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_ 11 mbz;
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lp 1 "Lower present";
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};
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constants ttype "Translation Type for requests-without-PASID" {
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hmd = 0b00 "Host mode with Device-TLBs disabled";
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hme = 0b01 "Host mode with Device-TLBs enabled";
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ptm = 0b10 "Pass-through mode";
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//0b011: reserved
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};
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constants addr_width "Address Width" {
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agaw30 = 0b000 "30-bit AGAW (2-level page table)";
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agaw39 = 0b001 "39-bit AGAW (3-level page table)";
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agaw48 = 0b010 "48-bit AGAW (4-level page table)";
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agaw57 = 0b011 "57-bit AGAW (5-level page table)";
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agaw64 = 0b100 "64-bit AGAW (6-level page table)";
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// 0b101-0b111 are reserved
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};
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// Context-entries have the same DID iff their SLPTPTR values are the same.
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datatype ctxt_entry "Context Entry" {
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_ 40 mbz;
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did 16 "Domain Identifier";
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_ 1 mbz;
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_ 4;
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aw 3 type(addr_width) "Address Width";
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slptptr 52 "Second Level Page Translation Pointer";
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_ 8 mbz;
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t 2 type(ttype) "Translation Type";
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fpd 1 "Fault Processing Disable";
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p 1 "Present";
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};
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datatype ext_ctxt_entry "Extended Context Entry" {
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pasidstptr 52 "PASID State Table Pointer";
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_ 12 mbz;
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pasidptr 52 "PASID Pointer Table";
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_ 8 mbz;
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pts 4 "PASID Table Size";
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pat 32 "Page Attribute Table";
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_ 4 mbz;
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slee 1 "Second-LEvel Execute Enable";
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ere 1 "Execute Requests Enable";
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eafe 1 "Extended Accessed Flag Enable";
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semp 1 "Supervisor Mode Execute Protection";
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did 16 "Domain Identifier";
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emte 1 "Extended Memory Type Enable";
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cd 1 "Cache Disable";
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wpe 1 "Write Protect Enable";
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nxe 1 "No Execute Enable";
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pge 1 "Page Global Enable";
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aw 3 "Address Width";
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slptptr 52 "Second Level Page Table Pointer";
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paside 1 "PASID Enable";
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neste 1 "NExted Translation Enable";
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pre 1 "Page Requeset Enable";
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dinve 1 "Deferred Invalidate Enable";
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emt 3 "Extended Memory Type";
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t 3 "Translatin Type";
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fpd 1 "Fault Processing Disable";
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p 1 "Present";
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};
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//////////////////////////// Remapping Registers ////////////////////////////
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register VER addr(base, 0x000) "Version Register" {
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_ 24 mbz;
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max 4 ro "Major Version number";
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min 4 ro "Minor Version number";
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};
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constants numdom "Number of domains supported" {
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nd4 = 0b000 "Hardware supports 4-bit (16 domains)";
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nd6 = 0b001 "Hardware supports 6-bit (64 domains)";
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nd8 = 0b010 "Hardware supports 8-bit (256 domains)";
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nd10 = 0b011 "Hardware supports 10-bit (1024 domains)";
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nd12 = 0b100 "Hardware supports 12-bit (4096 domains)";
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nd14 = 0b101 "Hardware supports 14-bit (16384 domains)";
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nd16 = 0b110 "Hardware supports 16-bit (65536 domains)";
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// 0b111 reserved
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};
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register CAP addr(base, 0x008) "Capability Register" {
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_ 3 rsvd;
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lp5 1 ro "Supports 5-level paging";
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pi 1 ro "Posted Interrupts Supported";
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_ 2 rsvd;
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fl1gp 1 ro "First Level 1-GByte Page Support";
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drd 1 ro "Read Draining";
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dwd 1 ro "Write Draining";
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mamv 6 ro "Maximum Address Mask Value";
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nfr 8 ro "Number of Fault-recording Registers";
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psi 1 ro "Page Selective Invalidation";
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_ 1 mbz;
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_ 2 mbz "Second Level Large Page Support - Reserved";
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sllps30 1 ro "Second Level Large Page Support - 1GB page size (30-bit offset to page frame)";
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sllps21 1 ro "Second Level Large Page Support - 2MB page size (21-bit offset to page frame)";
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fro 10 ro "Fault-recording Register offset";
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_ 1 rsvd;
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zlr 1 ro "Zero Length Read";
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mgaw 6 ro "Maximum Guest Address Width";
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_ 3 mbz;
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_ 1 mbz "Supported Adjusted Guest Address Widths - reserved";
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sagaw57 1 ro "Supported Adjusted Guest Address Widths - 57-bit AGAW (5-level page-table)";
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sagaw48 1 ro "Supported Adjusted Guest Address Widths - 48-bit AGAW (4-level page-table)";
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sagaw39 1 ro "Supported Adjusted Guest Address Widths - 39-bit AGAW (3-level page-table)";
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_ 1 mbz "Supported Adjusted Guest Address Widths - reserved";
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cm 1 ro "Caching Mode";
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phmr 1 ro "Protected High-Memory Region";
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plmr 1 ro "Protected Low-Memory Region";
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rwbf 1 ro "Required Write-Buffer Flushing";
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afl 1 ro "Advanced Fault Logging";
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nd 3 ro type(numdom) "Number of domains supported";
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};
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register ECAP addr(base, 0x010) "Extended Capability Register" {
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_ 22 mbz;
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pds 1 ro "Page-request drain";
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dit 1 ro "device TLB invalidation throttle";
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pss 5 ro "PASID Size Supported";
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eafs 1 ro "Extended Accessed Flag Support";
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nwfs 1 ro "No Write Flag Support";
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pot 1 ro "PASID-Only Translations";
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srs 1 ro "Supervisor Request Support";
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ers 1 ro "Execute Request Support";
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prs 1 ro "Page Request Support";
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pasid 1 ro "Process Address Space ID Support";
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dis 1 ro "Deferred Invalidate Support";
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nest 1 ro "Nested Translation Support";
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mts 1 ro "Memory Type Support";
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ecs 1 ro "Extended Context Support";
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mhmv 4 ro "Maximum Handle Mask Value";
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_ 2 mbz;
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iro 10 ro "IOTLB Register Offset";
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sc 1 ro "Snoop Control";
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pt 1 ro "Pass Through";
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_ 1 rsvd;
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eim 1 ro "Extended Interrupt Mode";
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ir 1 ro "Interrupt Remapping support";
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dt 1 ro "Device-TLB support";
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qis 1 ro "Queued Invalidation support";
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pwc 1 ro "Page-walk Coherency";
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};
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register GCMD addr(base, 0x018) "Global Command Register" {
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te 1 wo "Translation Enable";
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srtp 1 wo "Set Root Table Pointer";
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sfl 1 wo "Set Fault Log";
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eafl 1 wo "Enable Advanced Fault Logging";
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wbf 1 wo "Write Buffer Flush";
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qie 1 wo "Queued Invalidation Enable";
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ire 1 wo "Interrupt Remapping Enable";
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sirtp 1 wo "Set Interrupt Remap Table Pointer";
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cfi 1 wo "Compatibility Format Interrupt";
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_ 23 mbz;
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};
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register GSTS addr(base, 0x01C) "Global Status Register" {
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tes 1 ro "Translation Enable Status";
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rtps 1 ro "Root Table Pointer Status";
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fls 1 ro "Fault Log Status";
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afls 1 ro "Advanced Fault Logging Status";
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wbfs 1 ro "Write Buffer Flash Status";
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qies 1 ro "Queued Invalidation Enable Status";
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ires 1 ro "Interrupt Remapping Enable Status";
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irtps 1 ro "Interrupt Remaping Table Pointer Status";
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cfis 1 ro "Compatibility Format Interrupt Status";
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_ 23 mbz;
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};
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constants rtt_ "Root Table Type" {
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rt = 0x0 "Root Table";
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ert = 0x1 "Extended Root Table";
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};
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register RTADDR addr(base, 0x020) "Root Table Address Register" {
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rta 52 rw "Root Table Address";
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rtt 1 rw "Root Table Type";
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_ 11 mbz;
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};
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constants irg_ "Context Invalidation Request Granularity" {
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rsvd_ir = 0b00 "Reserved";
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gir = 0b01 "Global Invalidation request";
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domir = 0b10 "Domain-selective invalidation request";
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devir = 0b11 "Device-selective invalidation request";
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};
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constants aig_ "Context Actual Request Granularity" {
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rsvd_ip = 0b00 "Reserved";
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gip = 0b01 "Global Invalidation performed";
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domip = 0b10 "Domain-selective invalidation performed";
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devip = 0b11 "Device-selective invalidation performed";
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};
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constants functmask "Function Mask" {
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nomask = 0b00 "No bits in the SID field masked";
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mask2 = 0b01 "Mask bit 2 in the SID field";
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mask12 = 0b10 "Mask bits 2:1 in the SID field";
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mask012 = 0b11 "Mask bits 2:0 in the SID field";
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};
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register CCMD addr(base, 0x028) "Context Command Register" {
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icc 1 rw "Invalidate Context-Cache";
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cirg 2 rw type(irg_) "Context Invalidation Request Granularity";
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caig 2 ro type(aig_) "Context Actual Invalidation Granularity";
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_ 25 mbz;
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fm 2 wo type(functmask) "Function Mask";
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sid 16 wo "Source-ID";
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did 16 rw "Domain-ID";
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};
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register FSTS addr(base, 0x034) "Fault Status Register " {
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_ 16 rsvd;
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fri 8 rw1cs "Fault Record Index";
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pro 1 rw1cs "Page Request Overflow";
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ite 1 rw1cs "Invalidation Timeout Error";
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ice 1 rw1cs "Invalidation Completion Error";
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iqe 1 rw1cs "Invalidation Queue Error";
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apf 1 rw1cs "Advanced Pending Fault";
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afo 1 rw1cs "Advanced Fault Overflow";
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ppf 1 rw1cs "Primary Pending Fault";
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pfo 1 rw1cs "Primary Fault Overflow";
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};
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register FECTL addr(base, 0x038) "Fault Event Control Register" {
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im 1 rw "Interrupt mask";
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ip 1 ro "Interrupt Pending";
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_ 30 rsvd;
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};
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register FEDATA addr(base, 0x03C) "Fault Event Data Register" {
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eimd 16 rw "Extended Interrupt Message Data";
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imd 16 rw "Interrupt Message Data";
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};
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register FEADDR addr(base, 0x040) "Fault Event Address Register" {
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ma 30 rw "Message address";
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_ 2 rsvd;
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};
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register FEUADDR addr(base, 0x044) "Fault Event Upper Address Register" {
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mua 32 rw "Message upper address";
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};
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register AFLOG addr(base, 0x058) "Advanced Fault Log Register" {
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fla 52 rw "Fault log address";
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fls 3 rw "Fault log size in bits x 4K pages";
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_ 9 rsvd;
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};
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register PMEN addr(base, 0x064) "Protected Memory Enable Register" {
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epm 1 rw "Enable Protected memory";
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_ 30 rsvd;
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prs 1 ro "Protected Region Status";
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};
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register PLMBASE addr(base, 0x068) "Protected Low Memory Base Register" {
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plmb 20 rw "Protected Low-Memory Base";
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_ 12 rsvd;
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};
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register PLMLIMIT addr(base, 0x06C) "Protected Low Memory Limit Register" {
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plmb 20 rw "Protected Low-Memory Limit";
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_ 12 rsvd;
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};
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register PHMBASE addr(base, 0x070) "Protected High Memory Base Register" {
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phmb 52 rw "Protected High-Memory Base";
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_ 12 rsvd;
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};
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register PHMLIMIT addr(base, 0x078) "Protected High Memory Limit Register" {
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phml 52 rw "Protected High-Memory Limit";
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_ 12 rsvd;
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};
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register IQH addr(base, 0x080) "Invalidation Queue Head" {
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_ 46 rsvd;
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qh 14 ro "Queue Head";
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_ 4 rsvd;
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};
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register IQT addr(base, 0x088) "Invalidation Queue Tail" {
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_ 46 rsvd;
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qt 14 rw "Queue Tail";
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_ 4 rsvd;
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};
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register IQA addr(base, 0x090) "Invalidation Queue Address" {
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iqa 52 rw "Ivalidation Queue Base Address";
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_ 9 rsvd;
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qs 3 rw "Queue Size";
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};
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register ICS addr(base, 0x09C) "Invalidation Completion Status" {
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_ 31 rsvd;
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iwc 1 rw1cs "Invalidation Wait Descriptor Complete";
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};
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register IECTL addr(base, 0x0A0) "Invalidation Completion Event" {
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im 1 rw "Interrupt Mask";
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ip 1 ro "Interrupt Pending";
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_ 30 rsvd;
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};
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register IEDATA addr(base, 0x0A4) "Invalidation Completion Event Data" {
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eimd 16 rw "Extended Interrupt Message Data";
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imd 16 rw "Interrupt Message data";
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};
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register IEADDR addr(base, 0x0A8) "Invalidation Completion Event Address" {
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ma 30 rw "Message address";
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_ 2 rsvd;
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};
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register IEUADDR addr(base, 0x0AC) "Invalidation Completion Event Upper Address Register" {
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mua 32 rw "Message upper address";
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};
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register IRTA addr(base, 0x0B8) "Interrupt Remapping Table Address Register" {
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irta 52 rw "Interrupt Remapping Table Address";
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eime 1 rw "Extended Interrupt Mode Enable";
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_ 7 rsvd;
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s 4 rw "Size";
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};
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register PQH addr(base, 0x0C0) "Page Request Queue Head Register" {
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_ 46 rsvd;
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pqh 14 rw "Page Queue Head";
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_ 4 rsvd;
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};
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register PQT addr(base, 0x0C8) "Page Request Queue Tail Register" {
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_ 46 rsvd;
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pqt 14 rw "Page Queue Tail";
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_ 4 rsvd;
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};
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register PQA addr(base, 0x0D0) "Page Request Queue Address Register" {
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pqa 52 rw "Page Request Queue Base Address";
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_ 9 rsvd;
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pqs 3 rw "Pgae Queue Size";
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};
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register PRS addr(base, 0x0DC) "Page Request Status Register" {
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_ 31 rsvd;
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ppr 1 rw1cs "Pending Page Request";
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};
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register PECTL addr(base, 0x0E0) "Page Request Event Control Register" {
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im 1 rw "Interrupt mask";
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pe 1 ro "Interrupt Pending";
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_ 30 rsvd;
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};
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register PEDATA addr(base, 0x0E4) "Page Request Event Data Register" {
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eimd 16 rw "Extended Interrupt Message Data";
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imd 16 rw "Interrupt Message Data";
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};
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register PEADDR addr(base, 0x0E8) "Page Request Event Address Register" {
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ma 30 rw "Message address";
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_ 2 rsvd;
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};
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register PEUADDR addr(base, 0x0EC) "Page Request Event Upper Address Register" {
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mua 32 rw "Message upper address";
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};
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/* TODO: Memory Type Range Registers */
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////////////////////////////// IOTLB Registers //////////////////////////////
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register IVA addr(iotlb, 0x000) "Invalidate Address Register" {
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addr 52 wo "Address";
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_ 5 mbz;
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ih 1 wo "Invalidation Hint";
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am 6 wo "Address Mask";
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};
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register IOTLB addr(iotlb, 0x008) "IOTLB Invalidate Register" {
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ivt 1 rw "Invalidate IOTLB";
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_ 1 mbz;
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iirg 2 rw type(irg_) "IOTLB Invalidation Request Granularity";
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_ 1 mbz;
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iaig 2 ro type(aig_) "IOTLB Actual Invalidation Granularity";
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_ 7 mbz;
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dr 1 rw "Drain Reads";
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dw 1 rw "Drain Writes";
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did 16 rw "Domain-ID";
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_ 32 mbz;
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};
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///////////////////////// Fault Recording Registers /////////////////////////
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regarray FRCD_Lo addr(frr, 0x0) [256;16] "Fault Recording Register Lo" {
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fi 52 ros "Fault Info";
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_ 12 rsvd;
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};
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regarray FRCD_Hi addr(frr, 0x8) [256;16] "Fault Recording Register Hi" {
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f 1 rw1cs "Fault";
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t 1 ros "Type";
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at 2 ros "Address Type";
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pv 20 ros "PASID Value";
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fr 8 ros "Fault reason";
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pp 1 ros "PASID Present";
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exe 1 ros "Execute Permission Requested";
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priv 1 ros "Privilege Mode Requested";
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_ 13 rsvd;
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sid 16 ros "Source Identifier";
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};
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};
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