152 lines
3.8 KiB
Plaintext
152 lines
3.8 KiB
Plaintext
/*
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* Copyright (c) 2011, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaestr. 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* uhci.dev
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*
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* DESCRIPTION: Universal Host Controller Interface (UHCI) description
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*
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* Rather old hardware - provided primarily for compatibility with qemu.
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* Numbers in comments refer to the Intel Universal Host Controller
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* Interface (UHCI) Design Guide Revision 1.1., March 1996.
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*/
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device uhci msbfirst ( io base ) "UHCI USB controller" {
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// 2.1.1
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// Default value: 0x0000
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register usbcmd rw io(base, 0x0000) "USB command" {
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_ 8;
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maxp 1 "Max packet (1=64 bytes, 0=32 bytes)";
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cf 1 "Configure flag";
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swdbg 1 "Software debug";
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fgr 1 "Force global resume";
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egsm 1 "Enter global suspend mode";
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greset 1 "Global reset";
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hcreset 1 "Host controller reset";
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rs 1 "Run/stop";
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};
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// 2.1.2
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// Default value: 0x0000
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register usbsts rwc io(base, 0x0002) "USB status" {
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_ 10;
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hch 1 "Host controller halted";
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hcpe 1 "Host controller process error";
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hse 1 "Host system error";
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rd 1 "Resume detect";
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uei 1 "USB error interrupt";
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usbint 1 "USB interrupt";
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};
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// 2.1.3
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// Default value: 0x0000
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register usbintr rw io(base, 0x0004) "USB interrupt enable" {
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_ 12;
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sp 1 "Short packet interrupt enable";
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ioc 1 "Interrupt on complete enable";
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ri 1 "Resume interrupt enable";
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tc 1 "Timeout/CRC interrupt enable";
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};
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// 2.1.4
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// Default value: 0x0000
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register frnum rw io(base, 0x0006) "Frame number" {
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_ 5;
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flcifn 11 "Frame list current index / frame number";
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};
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// 2.1.5
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// Default value: undefined
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// Bottom 12 bits must be zero
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register flbaseadd rw io(base, 0x0008) "Frame list base address"
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type(uint32);
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// 2.1.6
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// Default value: 0x40
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// SOF cycle time = 11936 + softv; default gives 12k, which at
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// 12MHz gives 1ms frame period.
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register sof rw io(base, 0x000c) "Start of frame modify" {
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_ 1;
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softv 7 "SOF timing value";
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};
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// 2.1.7
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// Default values: 0x80
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regarray portsc io(base, 0x10)[ 2 ] "Port status and control" {
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_ 3;
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susp 1 rw "suspend";
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_ 2;
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pr 1 rw "port reset";
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lsda 1 ro "low-speed device attached";
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_ 1; // Always read as 1
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rd 1 rw "resume detect";
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ls 2 ro "line status";
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pedc 1 rw1c "port enable/disable change";
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ped 1 rw "port enabled/disabled";
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csc 1 rw1c "connect status change";
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ccs 1 ro "current connect status";
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};
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// 3.1
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datatype flp "Frame list pointer" {
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flp 28 "bits 31:4 of frame list pointer";
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_ 2 mbz;
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q 1 "QH/TD select";
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t 1 "terminate (frame list pointer not valid)";
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};
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// 3.2
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datatype td msbfirst(32) "Transfer descriptor" {
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// link (dword 0)
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lp 28 "bits 31:4 of link pointer";
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_ 1 mbz;
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vf 1 "Depth/breadth select";
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q 1 "QH/TD select";
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t 1 "terminate (link pointer is not valid)";
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// control and status (dword 1)
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_ 2;
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spd 1 "short packet detect";
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ec 2 "error count";
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ls 1 "low speed device";
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ios 1 "isochronous select";
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ioc 1 "interrupt on complete";
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// Bits 23:16 of second word are status, viz:
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active 1 "active";
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stalled 1 "stalled";
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dbe 1 "data buffer error";
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babble 1 "babble detected";
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nakr 1 "NAK received";
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cte 1 "CRC/Timeout error";
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bse 1 "bitstuff error";
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_ 1;
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_ 5;
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actlen 11 "actual length";
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// token (dword 2)
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maxlen 11 "maximum length";
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_ 1;
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d 1 "data toggle";
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endpt 4 "endpoint";
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devaddr 7 "device address";
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pid 8 "packet indentification";
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// buffer ptr (dword 3)
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buffer 32 "buffer pointer";
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};
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// 3.3
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datatype qhe msbfirst(32) "Queue head and element" {
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qelp 28 "bits 31:4 of queue head or element link pointer";
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_ 2 mbz;
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q 1 "QH/TD select";
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t 1 "terminate (qelp not valid)";
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};
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};
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