291 lines
8.0 KiB
Plaintext
291 lines
8.0 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* tulip.dev
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*
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* DESCRIPTION: DEC Tulip Ethernet controller
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*
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* Section numbers in this file refer to the DIGITAL Semiconductor
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* 21140A PCI Fast Ethernet LAN Controller Hardware Reference Manual,
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* available at http://www.intel.com/design/network/manuals/21140ahm.pdf
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*/
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device tulip lsbfirst ( io base ) "Tulip Ethernet Controller" {
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// 3.2.2.1
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register CSR0 rw io ( base, 0x00 ) "Bus mode" {
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SWR 1 "Software reset";
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BAR 1 "Bus arbitration";
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DSL 5 "Descriptor Skip Length";
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BLE 1 "Big/little endian";
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PBL 6 "Programmable burst length";
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CAL 2 "Cache alignment";
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_ 1 mbz;
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TAP 3 "Transmit auto polling";
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DBO 1 "Descriptor byte ordering mode";
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RME 1 "Read multiple enable";
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_ 1 mbz;
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RLE 1 "Read line enable";
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WIE 1 "Write and invalidation enable";
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_ 7 mbz;
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};
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// 3.2.2.2
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register CSR1 wo io( base, 0x08 ) "Transmit poll demand" type(uint32);
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// 3.2.2.3
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register CSR2 wo io( base, 0x10 ) "Receive poll demand" type(uint32);
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// 3.2.2.4
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register CSR3 rw io( base, 0x18 ) "Receive list base address" type(uint32);
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register CSR4 rw io( base, 0x20 ) "Transmit list base address" type(uint32);
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// 3.2.2.5
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constants FBEBITS "Fatal bus error bits" {
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parity = 0b000 "Parity error";
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mabrt = 0b001 "Master abort";
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tabrt = 0b010 "Target abort";
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};
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constants TPROCSTATE "Transmit process state" {
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tpstop = 0b000 "Stopped: reset cmd or tx jabber expired";
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tprftd = 0b001 "Running - fetching tx desc.";
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tprwet = 0b010 "Running - waiting for end of tx";
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tprrbm = 0b011 "Running - reading buf from mem & queuing tx fifo";
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tprset = 0b101 "Running - setup packet";
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tpsusp = 0b110 "Suspended - tx fifo underflow, or unavail tx desc";
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tprclo = 0b111 "Running - closing tx desc";
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};
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constants RPROCSTATE "Receive process state" {
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rpstop = 0b000 "Stopped: reset or stop rx command";
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rprfrd = 0b001 "Running - fetching rx desc.";
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rprcep = 0b010 "Running - checking for end of rx pkt";
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rprwrp = 0b011 "Running - waiting for rx packet";
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rpsusp = 0b100 "Suspected - unavailable rx buf";
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rprclo = 0b101 "Running - closing rx desc";
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rprflu = 0b110 "Running - flushing current frame (no rx buf)";
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rprqrf = 0b111 "Running - queueing rx frame to buf";
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};
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register CSR5 rw1c io( base, 0x28 ) "Status" {
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TI 1 "Transmit interrupt";
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TPS 1 "Transmit process stopped";
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TU 1 "Transmit buffer unavailable";
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TJT 1 "Transmit jabber timeout";
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_ 1 mbz;
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UNF 1 "Transmit underflow";
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RI 1 "Receive interrupt";
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RU 1 "Receive buffer unavailable";
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RPS 1 "Receive process stopped";
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RWT 1 "Receive watchdog timeout";
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ETI 1 "Early termination timeout";
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GTE 1 "General-purpose timer expired";
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_ 1 mbz;
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FBE 1 "Fatal bus error";
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ERI 1 "Early receive interrupt";
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AIS 1 "Abnormal interrupt summary";
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NIS 1 "Normal interrupt summary";
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RS 3 ro type(RPROCSTATE) "Receive process state";
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TS 3 ro type(TPROCSTATE) "Transmission process state";
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EB 3 ro type(FBEBITS) "Error bits";
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_ 6 mbz;
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} ;
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// 3.2.2.6
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register CSR6 rw io( base, 0x30 ) "Operating mode" {
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HP 1 "Hash/perfect recieve filtering mode";
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SR 1 "Start/stop receive";
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HO 1 "Hash-only filtering mode";
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PB 1 "Pass bad frames";
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IF 1 "Inverse filtering" ;
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SB 1 "Start/stop backoff counter";
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PR 1 "Promiscuous mode";
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PM 1 "Pass all multicast";
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_ 1 mbz;
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FD 1 "Full-duplex mode";
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OM 2 "Operating mode";
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FC 1 "Force collision mode";
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ST 1 "Start/stop transmission command";
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TR 2 "Threshold control bits";
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_ 1 mbz;
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CA 1 "Capture effect enable";
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PS 1 "Port select";
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HBD 1 "Heartbeat disable";
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_ 1 mbz;
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SF 1 "Store and forward";
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TTM 1 "Transmit threshold mode";
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PCS 1 "PCS function";
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SCR 1 "Scrambler mode";
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_ 1 mb1;
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_ 4 mbz;
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RA 1 "Receive all";
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SC 1 "Special capture effect enable";
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};
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// 3.2.2.7
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register CSR7 rw io( base, 0x38 ) "Interrupt enable" {
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TI 1 "Transmit interrupt enable";
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TS 1 "Transmit stopped enable";
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TU 1 "Transmit buffer unavailable enable";
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TJ 1 "Transmit jabber timeout enable";
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_ 1 mbz;
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UN 1 "Underflow interrupt enable";
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RI 1 "Recieve interrupt enable";
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RU 1 "Recieve buffer unavailable enable";
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RS 1 "Recieve stopped enable";
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RW 1 "Recieve watchdog timeout enable";
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ETE 1 "Early transmit interrupt enable";
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GPT 1 "General-purpose timer enable";
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_ 1 mbz;
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FBE 1 "Fatal bus error enable";
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ERE 1 "Early receive enable";
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AI 1 "Abnormal interrupt summary enable";
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NI 1 "Normal interrupt summary enable";
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_ 15 mbz;
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};
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// 3.2.2.8
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register CSR8 ro io( base, 0x40 ) "Missed frames and overflow counter" {
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MFC 16 "Missed frame counter";
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MFO 1 "Missed frame overflow";
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FOC 11 "FIFO overflow counter";
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OCO 1 "Overflow counter overflow";
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_ 3 mbz;
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};
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// 3.2.2.9
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register CSR9 rw io( base, 0x48 ) "Boot ROM Management" {
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DATA 8 "Boot ROM data or serial ROM control";
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_ 2 mbz;
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REG 1 "External register select";
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SR 1 "Serial ROM select";
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BR 1 "Boot ROM select";
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WR 1 "ROM write operation";
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RD 1 "ROM read operation";
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_ 1 mbz;
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MDC 1 "MII management clock";
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MDO 1 "MII management write data";
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MII 1 "MII management operation mode";
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MDI 1 "MII management data_in";
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_ 12 mbz;
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};
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// 3.2.2.10
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register CSR10 rw io( base, 0x50 ) "Boot ROM programming address" {
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VAL 18 "Boot ROM address";
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_ 14 mbz;
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};
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// 3.2.2.11
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register CSR11 rw io( base, 0x58 ) "General-purpose timer" {
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VAL 16 "Timer value";
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CON 1 "Continuous mode";
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_ 15 mbz;
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};
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// 3.2.2.12
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register CSR12 rw io( base, 0x60 ) "General purpose port" {
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MD 8 "General-purpose mode and data";
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GPC 1 "General-purpose control";
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_ 23 mbz;
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};
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// 3.2.2.13
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register CSR15 rw io( base, 0x78 ) "Watchdog timer" {
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JBD 1 "Jabber disable";
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HUJ 1 "Host unjab";
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JCK 1 "Jabber clock";
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_ 1 mbz;
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RWD 1 "Receive watchdog disable";
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RWR 1 "Receive watchdog release";
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_ 26;
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};
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// 4.2.1
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constants FRAMEDTYPE width(2) "Frame data type" {
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sr = 0b00 "Serial received frame";
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il = 0b01 "Internal loopback frame";
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el = 0b10 "External loopback or serial received frame";
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};
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datatype RDES msbfirst(32) "Receive descriptor" {
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// RDES0
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OWN 1 "Own bit";
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FF 1 "Filtering fail";
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FL 14 "Frame length";
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ES 1 "Error summary";
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DE 1 "Descriptor error";
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DT 2 type(FRAMEDTYPE) "Data type";
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RF 1 "Runt Frame";
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MF 1 "Muticast frame";
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FS 1 "First descriptor";
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LS 1 "Last descriptor";
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TL 1 "Frame too long";
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CS 1 "Collision seen";
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FT 1 "Frame type";
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RW 1 "Receive watchdog";
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RE 1 "Report on MII error";
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DB 1 "Dribbling bit";
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CE 1 "CRC error";
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ZERO 1 "Zero";
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// RDES1
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_ 6;
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RER 1 "Receive end of ring";
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RCH 1 "Second address chained";
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_ 2;
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RBS2 11 "Buffer 2 size";
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RBS1 11 "Buffer 1 size";
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// RDES2-3
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RBA1 32 "Buffer address 1";
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RBA2 32 "Buffer address 2";
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};
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// 4.2.2
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datatype TDES msbfirst(32) "Transmit descriptor" {
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// TDES0
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OWN 1 "Own bit";
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_ 15;
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ES 1 "Error summary";
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TO 1 "Transmit jabber timeout";
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_ 2;
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LO 1 "Loss of Carrier";
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NC 1 "No Carrier";
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LC 1 "Late Collision";
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EC 1 "Excessive Collisions";
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HF 1 "Heartbeat Fail";
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CC 4 "Collision Count";
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LF 1 "Link Fail Report";
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UF 1 "Underflow Error";
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DE 1 "Deferred";
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// TDES1
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IC 1 "Interrupt on Completion";
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LS 1 "Last Segment";
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FS 1 "First Segment";
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FT1 1 "Filtering Type";
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SET 1 "Setup Packet";
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AC 1 "Add CRC Disable";
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TER 1 "Transmit End of Ring";
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TCH 1 "Second Address Chained";
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DPD 1 "Disabled Padding";
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FT0 1 "Filtering Type";
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TBS2 11 "Buffer 2 Size";
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TBS1 11 "Buffer 1 Size";
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// TDES2-3
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TBA1 32 "Buffer address 1";
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TBA2 32 "Buffer address 2";
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};
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// Table 4-8: This value is split between FT0 and FT1 above.
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// Unfortunately (unlike Devil) Mackerel can't express this
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// cleanly (yet).
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constants FILTERTYPE width(2) "Filtering type" {
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PF = 0b00 "Perfect filtering";
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HF = 0b01 "Hash-based filtering";
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IF = 0b10 "Inverse filtering";
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HOF = 0b11 "Hash-only filtering";
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};
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};
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