303 lines
11 KiB
Plaintext
303 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* ti_i2c.dev
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*
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* DESCRIPTION: TI I2C controller registers.
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*
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* Section numbers refer to OMAP4460 ES1.x PUBLIC TRM vQ
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*
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* (I think the I2C controllers in the OMAP4460 match the standard TI I2C) -SG
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*/
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device ti_i2c msbfirst (addr b) "TI I2C controller" {
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// Tables 23-33 and 23-35
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register revnb_lo ro addr(b, 0x0) "Revision number (low part)" type(uint16);
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register revnb_hi ro addr(b, 0x4) "Revision number (high part)" type(uint16);
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constants clkact "clock activity" {
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clk_off = 0b00 "Both clocks can be off";
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clk_ocp = 0b01 "Only OCP clock must be kept active";
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clk_sys = 0b10 "Only system clock must be kept active";
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clk_act = 0b11 "Both clocks must be active";
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};
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constants idlemode "idle mode" {
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idlemode_forceidle = 0b00 "Force Idle";
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idlemode_noidle = 0b01 "No Idle";
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idlemode_smartidle = 0b10 "Smart Idle";
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idlemode_smartwkup = 0b11 "Smart Idle & Wakeup";
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};
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// Table 23-37
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register sysc rw addr(b, 0x10) "System Configuration" {
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_ 6 rsvd;
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clkactivity 2 type(clkact) "Clock activity selection";
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_ 3 rsvd;
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idlemode 2 type(idlemode) "Idle mode selection";
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enawakeup 1 "Enable wakeup control";
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srst 1 "SoftReset";
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autoidle 1 "Autoidle";
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};
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// Tables 23-39 and 23-41
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regtype irqstatus "interrupt status vector" {
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_ 1 rsvd;
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xdr 1 "Transmit draining";
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rdr 1 "Receive draining";
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bb 1 ro "Bus busy";
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rovr 1 "Receive overrun";
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xudf 1 "Transmit underflow";
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aas 1 "Address recognized as slave IRQ status";
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bf 1 "Bus free";
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aerr 1 "Access error";
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stc 1 "Start condition";
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gc 1 "General call";
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xrdy 1 "Transmit data ready";
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rrdy 1 "Receive data ready";
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ardy 1 "Register access ready";
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nack 1 "No acknowledgement";
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al 1 "Arbitration lost";
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};
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register irqstatus_raw rw addr(b, 0x24) "Per-event raw interrupt status vector"
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type(irqstatus);
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register irqstatus rw1c addr(b, 0x28) "Per-event enabled interrupt status vector"
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type(irqstatus);
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// Tables 23-43 and 23-45
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regtype irqenable "interrupt enable vector" {
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_ 1 rsvd;
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xdr_ie 1 "Transmit draining";
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rdr_ie 1 "Receive draining";
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_ 1 rsvd;
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// NOTE: rovr and xudf don't have _ie in OMAP TRM -SG
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rovr_ie 1 "Receive overrun";
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xudf_ie 1 "Transmit underflow";
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aas_ie 1 "Address recognized as slave IRQ status";
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bf_ie 1 "Bus free";
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aerr_ie 1 "Access error";
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stc_ie 1 "Start condition";
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gc_ie 1 "General call";
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xrdy_ie 1 "Transmit data ready";
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rrdy_ie 1 "Receive data ready";
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ardy_ie 1 "Register access ready";
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nack_ie 1 "No acknowledgement";
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al_ie 1 "Arbitration lost";
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};
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register irqenable_set rw addr(b, 0x2C) "Per-event interrupt enable bit vector"
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type(irqenable);
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register irqenable_clr rw addr(b, 0x30) "Per-event interrupt clear bit vector"
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type(irqenable);
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regtype wakeupen "per-event wakeup enable" {
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_ 1 rsvd;
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xdr 1 "Transmit draining";
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rdr 1 "Receive draining";
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_ 1 rsvd;
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rovr 1 "Receive overrun";
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xudf 1 "Transmit underflow";
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aas 1 "Address recognized as slave IRQ status";
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bf 1 "Bus free";
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_ 1 rsvd;
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stc 1 "Start condition";
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gc 1 "General call";
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_ 1 rsvd;
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drdy 1 "Receive/Transmit data ready";
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ardy 1 "Register access ready";
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nack 1 "No acknowledgement";
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al 1 "Arbitration lost";
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};
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// Table 23-47
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register we rw addr(b, 0x34) "Wakeup enable vector" type(wakeupen);
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// Tables 23-49, 23-51, 23-53, and 23-55
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// NOTE: nomenclature doesn't match OMAP TRM
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regtype dmaen "DMA enable" {
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_ 15 rsvd;
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en 1 "Enable DMA channel";
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};
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register dmarxenable_set addr(b, 0x38) "Per-event DMA RX enable"
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type(dmaen);
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register dmatxenable_set addr(b, 0x3C) "Per-event DMA TX enable"
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type(dmaen);
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register dmarxenable_clr addr(b, 0x40) "Per-event DMA RX enable clear"
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type(dmaen);
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register dmatxenable_clr addr(b, 0x44) "Per-event DMA TX enable clear"
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type(dmaen);
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// Tables 23-57 and 23-59
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register dmarxwake_en addr(b, 0x48) "Per-event DMA RX wakeup enable"
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type(wakeupen);
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register dmatxwake_en addr(b, 0x4C) "Per-event DMA TX wakeup enable"
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type(wakeupen);
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// Table 23-61
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register ie rw addr(b, 0x84) "Interrupt enable vector (legacy)"
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type(irqenable);
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// dummy constants for polling stat flags
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constants irqstatus_flags width(16) "irqstatus bitmasks" {
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irq_flag_xdr = 0x4000 "Transmit draining";
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irq_flag_rdr = 0x2000 "Receive draining";
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irq_flag_bb = 0x1000 "Bus busy";
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irq_flag_rovr = 0x0800 "Receive overrun";
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irq_flag_xudf = 0x0400 "Transmit underflow";
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irq_flag_aas = 0x0200 "Address recognized as slave IRQ status";
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irq_flag_bf = 0x0100 "Bus free";
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irq_flag_aerr = 0x0080 "Access error";
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irq_flag_stc = 0x0040 "Start condition";
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irq_flag_gc = 0x0020 "General call";
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irq_flag_xrdy = 0x0010 "Transmit data ready";
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irq_flag_rrdy = 0x0008 "Receive data ready";
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irq_flag_ardy = 0x0004 "Register access ready";
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irq_flag_nack = 0x0002 "No acknowledgement";
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irq_flag_al = 0x0001 "Arbitration lost";
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};
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// Table 23-63
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register stat rw1c addr(b, 0x88) "Interrupt status vector (legacy)"
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type(irqstatus);
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// Table 23-65
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register syss rw addr(b, 0x90) "System status" {
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_ 15 rsvd;
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rdone 1 rw "Reset done";
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};
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// Table 23-67
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register buf rw addr(b, 0x94) "Buffer Configuration" {
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rdma_en 1 "Receive DMA enable";
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rxfifo_clr 1 "Receive FIFO clear";
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rxtrsh 6 "Threshold value for FIFO buffer in RX mode";
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xdma_en 1 "Transmit DMA enable";
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txfifo_clr 1 "Transmit FIFO clear";
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txtrsh 6 "Threshold value for FIFO buffer in TX mode";
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};
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// Table 23-69
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// NOTE: writing 0 to cnt equals to a transfer of 65536 bytes; this means
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// that software has to disallow 0-byte transfers. -SG
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register cnt rw addr(b, 0x98) "Data counter" type(uint16);
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// Table 23-71
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register data rw addr(b, 0x9C) "Data access" {
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_ 8 rsvd;
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data 8 "Transmit/Receive data FIFO endpoint";
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};
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// Table 23-73
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constants opmode "Operation Mode" {
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opmode_fs = 0b00 "I2C Fast/Standard Mode";
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opmode_hs = 0b01 "I2C High Speed Mode";
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opmode_sccb = 0b10 "SCCB Mode";
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};
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register con rw addr(b, 0xA4) "Configuration" {
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en 1 "module enable";
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_ 1 rsvd;
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opmode 2 type(opmode) "Operation mode selection";
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stb 1 "Start byte mode";
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mst 1 "Master/slave mode";
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trx 1 "Transmitter/Receiver mode";
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xsa 1 "Expand Slave Address";
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xoa0 1 "Expand Own address 0";
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xoa1 1 "Expand Own address 1";
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xoa2 1 "Expand Own address 2";
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xoa3 1 "Expand Own address 3";
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_ 2 rsvd;
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stp 1 "Stop condition";
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stt 1 "Start condition";
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};
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// Table 23-75
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register oa rw addr(b, 0xA8) "Own address" {
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mcode 3 "Master Code";
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_ 3 rsvd;
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oa 10 "Own addres";
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};
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// Table 23-77
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register sa rw addr(b, 0xAC) "Slave address" {
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_ 6 rsvd;
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sa 10 "Slave address";
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};
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// Table 23-79
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register psc rw addr(b, 0xB0) "Clock Prescaler" {
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_ 8 rsvd;
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psc 8 "Fast/Standard mode prescale sampling clock divider [/(psc+1)]";
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};
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// Tables 23-81 and 23-83
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regtype scltime "SCL time" {
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hsscl 8 "High Speed mode SCL time";
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scl 8 "Fast/Standard mode SCL time";
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};
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register scll rw addr(b, 0xB4) "SCL Low Time" type(scltime);
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register sclh rw addr(b, 0xB8) "SCL High Time" type(scltime);
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// Table 23-85
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constants testmode "Test mode" {
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test_functional = 0b00 "Functional mode (default)";
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test_loopback = 0b11 "Loop back mode select + SDA/SCL IO mode select";
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test_sclcnttest = 0b10 "Test of SCL counters";
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};
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register systest rw addr(b, 0xBC) "System Test" {
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st_en 1 "System test enable";
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free 1 "Free running mode (on breakpoint)";
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tmode 2 type(testmode) "Test mode select";
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ssb 1 "Set status bits from 0 to 14";
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_ 2 rsvd;
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scl_i_func 1 ro "SCL line input value";
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scl_o_func 1 ro "SCL line output value";
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sda_i_func 1 ro "SDA line input value";
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sda_o_func 1 ro "SDA line output value";
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sccb_e_o 1 rw "SCCB_E line sense output value";
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scl_i 1 ro "SCL line sense input value";
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scl_o 1 rw "SCL line drive output value";
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sda_i 1 ro "SDA line sense input value";
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sda_o 1 rw "SDA line drive output value";
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};
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// Table 23-87
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register bufstat ro addr(b, 0xC0) "Buffer Status" {
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fifodepth 2 "Internal FIFO buffers depth";
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rxstat 6 "RX buffer status";
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_ 2 rsvd;
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txstat 6 "TX buffer status";
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};
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// Tables 23-89, 23-91, and 23-93
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regtype ownaddr "own address" {
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_ 6 rsvd;
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oa 10 "Own address";
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};
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register oa1 addr(b, 0xC4) "Own Address 1" type(ownaddr);
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register oa2 addr(b, 0xC8) "Own Address 2" type(ownaddr);
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register oa3 addr(b, 0xCC) "Own Address 3" type(ownaddr);
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// Table 23-95
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register actoa ro addr(b, 0xD0) {
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_ 12 rsvd;
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oa3_act 1 "Own address 3 active";
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oa2_act 1 "Own address 2 active";
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oa1_act 1 "Own address 1 active";
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oa0_act 1 "Own address 0 active";
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};
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// Table 23-97
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register sblock rw addr(b, 0xD4) "Clock Blocking Enable" {
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_ 12 rsvd;
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oa3_en 1 "Own address 3 clock blocking enable";
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oa2_en 1 "Own address 2 clock blocking enable";
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oa1_en 1 "Own address 1 clock blocking enable";
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oa0_en 1 "Own address 0 clock blocking enable";
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};
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};
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