106 lines
3.2 KiB
Plaintext
106 lines
3.2 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* sp804_pit.dev
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*
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* DESCRIPTION: Dual-Timer Module SP804
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*
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* This is derived from:
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*
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* ARM Dual-Timer Module (SP804) Technical Reference Manual
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* (DDI0271_sp804_timer_trm.pdf)
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*
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*/
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device sp804_pit msbfirst ( addr base ) "Dual-Timer Module SP804" {
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constants prescale "Possible Prescale Values" {
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prescale0 = 0b00 "0 stages of prescale, clock divided by 1";
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prescale4 = 0b01 "4 stages of prescale, clock divided by 16";
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prescale8 = 0b10 "8 stages of prescale, clock divided by 256";
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};
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constants timer_size "Timer operation sizes" {
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size_16bit = 0b0 "16-bit counter";
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size_32bit = 0b1 "32-bit counter";
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};
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constants timer_modes "Timer Running Mode" {
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free = 0b0 "Counts once and then wraps to 0xffff";
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periodic = 0b1 "Reloads from load register at end of each count";
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};
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//
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// timer 1
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//
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register Timer1Load addr(base, 0x0) "Load Register" type(uint32);
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register Timer1Value ro addr(base, 0x4) "Current Value Register" type(uint32);
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register Timer1Control addr(base, 0x8) "Control Register" {
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_ 24 rsvd;
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timer_en 1 rw "Enable Bit";
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timer_mode 1 rw "Mode Bit";
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int_enable 1 rw "Interrupt Enable Bit";
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_ 1 rsvd;
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timer_pre 2 rw "Prescale Bits";
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timer_size 1 rw "Selects 16/32 bit mode";
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one_shot 1 rw "Selects one-shot or wrapping counter mode";
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};
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register Timer1IntClr wo addr(base, 0xc) "Interrupt Clear Register" type(uint32);
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register Timer1RIS ro addr(base, 0x10) "Raw Interrupt Status Register" {
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_ 31 rsvd;
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ri_status 1 ro "Raw interrupt status from the counter";
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};
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register Timer1MIS ro addr(base, 0x14) "Masked Interrupt Status Register" {
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_ 31 rsvd;
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mi_status 1 ro "Masked interrupt status from the counter";
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};
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register Timer1BGLoad addr(base, 0x18) "Background Load Register" type(uint32);
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//
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// timer 2
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//
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register Timer2Load addr(base, 0x20) "Load Register" type(uint32);
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register Timer2Value ro addr(base, 0x24) "Current Value Register" type(uint32);
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register Timer2Control addr(base, 0x28) "Control Register" {
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_ 24 rsvd;
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timer_en 1 rw "Enable Bit";
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timer_mode 1 rw "Mode Bit";
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int_enable 1 rw "Interrupt Enable Bit";
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_ 1 rsvd;
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timer_pre 2 rw "Prescale Bits";
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timer_size 1 rw "Selects 16/32 bit mode";
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one_shot 1 rw "Selects one-shot or wrapping counter mode";
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};
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register Timer2IntClr wo addr(base, 0x2c) "Interrupt Clear Register" type(uint32);
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register Timer2RIS ro addr(base, 0x30) "Raw Interrupt Status Register" {
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_ 31 rsvd;
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ri_status 1 ro "Raw interrupt status from the counter";
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};
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register Timer2MIS ro addr(base, 0x34) "Masked Interrupt Status Register" {
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_ 31 rsvd;
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mi_status 1 ro "Masked interrupt status from the counter";
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};
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register Timer2BGLoad addr(base, 0x38) "Background Load Register" type(uint32);
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}; |