206 lines
7.7 KiB
Plaintext
206 lines
7.7 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstr 6, CH-8092 Zurich.
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* Attn: Systems Group.
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*/
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/*
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* pl390_gic.dev
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*
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* DESCRIPTION: PrimeCell PL390 Generic Interrupt Controller
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*
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* This is derived from:
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*
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* [1] PrimeCell Generic Interrupt Controller PL390
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* (DDI0416B_gic_pl390_r0p0_trm.pdf)
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* [2] ARM Cortex A9 MPCore TRM r2p0
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* [3] ARM Generic Interrupt Controller v1.0
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*
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* Updated to work on PandaBoard according to [2] Table 3-1
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*
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* Register map for distributor: [3], chp 4.1.2
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* Register map for CPU interface: [3], chp 4.1.3
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*/
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device pl390_gic_dist msbfirst (addr dist_base)
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"PrimeCell PL390 Generic Interrupt Controller Distributor"
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{
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//
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// Distributor register map
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//
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register ICDDCR addr(dist_base, 0x0) "Distributor Control" {
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_ 31 rsvd;
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enable 1 rw "enable forwarding to CPU interface";
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};
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register ICDICTR ro addr(dist_base, 0x4) "Interrupt Controller Type" {
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_ 16;
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LSPI 5 "maximum number of lockable SPIs";
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TZ 1 "GIC implements Security Extensions";
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_ 2;
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cpu_number 3 "number of implemented CPU interfaces";
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it_lines_num 5 "max. num. (N) interrupts supported 32(N+1)";
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};
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register ICDIIDR ro addr(dist_base, 0x8) "Distributor Implementer Ident." {
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product_id 8 "Product identifier";
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rev_num 12 "Revision number";
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implementer 12 "JEP106 code of implementing company";
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};
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// Do not read 16 Bit values, only 32 bit ones, otherwise the
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// Mackerel code will crash on the PandaBoard
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regarray ICDISR addr(dist_base, 0x80) [32] "SPI Interrupt Security"
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type(uint32);
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regarray ICDISER addr(dist_base, 0x100) [32] "Interrupt Set-Enable"
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type(uint32);
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regarray ICDICER addr(dist_base, 0x180) [32] "Interrupt Clear-Enable"
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type(uint32);
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regarray ICDISPR addr(dist_base, 0x200) [32] "Interrupt Set-Pending"
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type(uint32);
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regarray ICDICPR addr(dist_base, 0x280) [32] "Interrupt Clear-Pending"
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type(uint32);
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regarray ICDABR ro addr(dist_base, 0x300) [32] "Interrupt Active Bit"
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type(uint32);
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regtype priority_reg "Interrupt priority register" {
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prio_off3 8 rw "Priority, byte offset 3";
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prio_off2 8 rw "Priority, byte offset 2";
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prio_off1 8 rw "Priority, byte offset 1";
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prio_off0 8 rw "Priority, byte offset 0";
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};
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regarray ICDIPR addr(dist_base, 0x400) [31] "Priority Level"
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type(priority_reg);
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regtype cpu_targets_reg "CPU targets" {
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targets_off3 8 rw "CPU targets, byte offset 3";
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targets_off2 8 rw "CPU targets, byte offset 2";
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targets_off1 8 rw "CPU targets, byte offset 1";
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targets_off0 8 rw "CPU targets, byte offset 0";
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};
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regarray ICDIPTR rw addr(dist_base, 0x800) [31] // only partly rw
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"Interrupt Processor Targets"
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type(cpu_targets_reg);
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regtype conf_reg "Configuration registers" {
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conf15 2 "Configuration 15";
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conf14 2 "Configuration 14";
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conf13 2 "Configuration 13";
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conf12 2 "Configuration 12";
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conf11 2 "Configuration 11";
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conf10 2 "Configuration 10";
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conf9 2 "Configuration 9";
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conf8 2 "Configuration 8";
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conf7 2 "Configuration 7";
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conf6 2 "Configuration 6";
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conf5 2 "Configuration 5";
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conf4 2 "Configuration 4";
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conf3 2 "Configuration 3";
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conf2 2 "Configuration 2";
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conf1 2 "Configuration 1";
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conf0 2 "Configuration 0";
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};
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regarray ICDICR rw addr(dist_base, 0xC00) [16]
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"Interrupt Configuration Reigsters"
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type(conf_reg);
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register PPI_STATUS ro addr(dist_base, 0xd00) "PPI Status" {
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_ 16;
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ppi_status 16 "Status of PPI0 - PPI15";
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};
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regarray SPI_STATUS ro addr(dist_base, 0xd04) [30] "SPI Status"
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type(uint32);
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register ICDSGIR wo addr(dist_base, 0xf00) "Software Generated Interrupt" {
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_ 6 mbz;
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target_list_filter 2 "Target List Filter";
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cpu_target_list 8 "CPU Target List";
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SATT 1 "Secure Access Bit";
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_ 11 mbz;
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SGIINTID 4 "SGI Interrupt ID";
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};
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register DIST_PERIPH_ID0 ro addr(dist_base, 0xfec) "Peripheral Ident. 0" {
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_ 24;
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part_number_0 8 "Part Number 0";
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};
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register DIST_PERIPH_ID1 ro addr(dist_base, 0xfe8) "Peripheral Ident. 1" {
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_ 24;
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jep106_id_3_0 4 "JEP106 identity code [3:0]";
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part_number_1 4 "Part Number 1";
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};
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register DIST_PERIPH_ID2 ro addr(dist_base, 0xfe4) "Peripheral Ident. 2" {
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_ 24;
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architecure 4 "Architecture vers. of GIC";
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jedec_used 1 "is ID allocated by JEDEC";
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jep106_id_6_4 3 "JEP106 identity code [6:4]";
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};
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register DIST_PERIPH_ID3 ro addr(dist_base, 0xfe0) "Peripheral Ident. 3" {
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_ 24;
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rev_and 4 "Revision of AND Gates";
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mod_number 4 "Modification Number";
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};
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register DIST_PERIPH_ID4 ro addr(dist_base, 0xfdc) "Peripheral Ident. 4" {
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_ 24;
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page_count 4 "# of 4KB blocks needed";
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jep106_c_code 4 "JEP106 continuation code";
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};
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register DIST_PERIPH_ID5 ro addr(dist_base, 0xfd8) "Peripheral Ident. 5" {
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_ 24;
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ppi_number_0 4 "LSBs of # of PPIs in FIC";
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sgi_number 4 "# of SGIs in GIC";
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};
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register DIST_PERIPH_ID6 ro addr(dist_base, 0xfd4) "Peripheral Ident. 6" {
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_ 24;
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spi_number_0 4 "LSBs of #SPIs GIC provides";
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ppi_number_1 4 "MSBs of #PPIs GIC provides";
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};
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register DIST_PERIPH_ID7 ro addr(dist_base, 0xfd0) "Peripheral Ident. 7" {
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_ 24;
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tz 1 "# secure states";
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priority 3 "# priority lvls GIC provides";
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spi_number_1 4 "MSBs of # SPIs GIC provides";
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};
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register DIST_PERIPH_ID8 ro addr(dist_base, 0xfc0) "Peripheral Ident. 8" {
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_ 24;
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identifier 1 "AMBA interface ID";
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if_type 2 "AMBA protocoll";
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cpu_if 3 "# of CPU interfaces";
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fiq_legacy 1 "Legacy FIQ signals supported";
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irq_legacy 1 "Legacy IRQ signals supported";
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};
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register DIST_COMPONENT_ID0 ro addr(dist_base, 0xffc) "PrimeCell Ident. 0" {
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_ 24;
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component_id 8;
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};
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register DIST_COMPONENT_ID1 ro addr(dist_base, 0xff8) "PrimeCell Ident. 1" {
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_ 24;
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component_id 8;
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};
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register DIST_COMPONENT_ID2 ro addr(dist_base, 0xff4) "PrimeCell Ident. 2" {
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_ 24;
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component_id 8;
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};
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register DIST_COMPONENT_ID3 ro addr(dist_base, 0xff0) "PrimeCell Ident. 3" {
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_ 24;
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component_id 8;
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};
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};
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