270 lines
8.7 KiB
Plaintext
270 lines
8.7 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* pl011_uart.dev
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*
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* DESCRIPTION: PrimeCell UART (PL011)
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*
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* This is derived from:
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*
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* PrimeCell UART (PL011) Revision: r1p5 by ARM Limited.
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* (DDI0183_uart_pl011_r1p5_trm.pdf)
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*
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*/
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device pl011_uart msbfirst ( addr base ) "PL011 UART" {
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constants word_len "Word Length" {
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bits5 = 0b00 "5 bits";
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bits6 = 0b01 "6 bits";
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bits7 = 0b10 "7 bits";
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bits8 = 0b11 "8 bits";
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};
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constants rx_lvl "Receive interrupt FIFO level" {
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geq_1_8 = 0b000;
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geq_1_4 = 0b001;
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geq_1_2 = 0b010;
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geq_3_4 = 0b011;
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geq_7_8 = 0b100;
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};
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constants tx_lvl "Transmit interrupt FIFO level" {
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leq_1_8 = 0b000;
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leq_1_4 = 0b001;
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leq_1_2 = 0b010;
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leq_3_4 = 0b011;
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leq_7_8 = 0b100;
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};
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/*
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* Standard UART registers
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*/
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register DR addr (base, 0x0) "Data Register" {
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_ 20;
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oe 1 ro "Overrun error";
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be 1 ro "Break error";
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pe 1 ro "Parity error";
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fe 1 ro "Framing error";
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data 8 rw "Data character";
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};
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register RSR_ECR addr (base, 0x4) "UART receive status / error clear" {
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_ 24;
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_ 4 rsvd;
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oe 1 rwzc "Overrun error";
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be 1 rwzc "Break error";
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pe 1 rwzc "Parity error";
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fe 1 rwzc "Framing error";
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};
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register FR addr (base, 0x18) "Flag Register" {
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_ 23;
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ri 1 ro "Ring indicator";
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txfe 1 ro "Transmit FIFO empty";
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rxff 1 ro "Receive FIFO full";
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txff 1 ro "Transmit FIFO full";
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rxfe 1 ro "Receive FIFO empty";
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busy 1 ro "UART Busy (transmit active)";
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dcd 1 ro "Data carrier detect";
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dsr 1 ro "Data set ready.";
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cts 1 ro "Clear to send.";
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};
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register ILPR addr (base, 0x20) "IrDA Low-Power Counter" {
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_ 24;
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ilpdvsr 8 rw "Low power divisor";
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};
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register IBRD addr (base, 0x24) "Integer Baud Rate" {
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_ 16;
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divint 16 rw "Integer divisor";
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};
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register FBRD addr (base, 0x28) "Fractional Baud Rate" {
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_ 26;
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divfrac 6 rw "Fractional divisor";
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};
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register LCR_H addr (base, 0x2c) "Line Control" {
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_ 24;
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sps 1 rw "Stick parity select";
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wlen 2 rw type(word_len) "Word length";
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fen 1 rw "FIFOs enable";
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stp2 1 rw "Two stop bits select";
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eps 1 rw "Even parity select";
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pen 1 rw "Parity enable";
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brk 1 rw "Send break";
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};
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register CR addr (base, 0x30) "Control" {
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_ 16;
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ctsen 1 rw "CTS hardware flow control enable";
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rtsen 1 rw "RTS hardware flow control enable";
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out2 1 rw "Out2 modem status output";
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out1 1 rw "Out1 modem status output";
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rts 1 rw "Request to send";
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dtr 1 rw "Data transmit ready";
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rxe 1 rw "Receive enable";
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txe 1 rw "Transmit enable";
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lbe 1 rw "Loopback enable";
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_ 4;
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sirlp 1 rw "SIR low-power IrDA mode";
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siren 1 rw "SIR enable";
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uarten 1 rw "UART enable";
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};
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register IFLS addr (base, 0x34) "Interrupt FIFO Level Select" {
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_ 26;
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rxiflsel 3 rw type(rx_lvl) "Receive interrupt FIFO level select";
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txiflsel 3 rw type(tx_lvl) "Transmit interrupt FIFO level select";
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};
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register IMSC addr (base, 0x38) "Interrupt Mask Set/Clear" {
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_ 21;
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oeim 1 rw "Overrun error interrupt mask";
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beim 1 rw "Break error interrupt mask";
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peim 1 rw "Parity error interrupt mask";
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feim 1 rw "Framing error interrupt mask";
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rtim 1 rw "Receive timeout interrupt mask";
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txim 1 rw "Transmit interrupt mask";
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rxim 1 rw "Receive interrupt mask";
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dsrmim 1 rw "nUARTDSR modem interrupt mask";
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dcdmim 1 rw "nUARTDCD modem interrupt mask";
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ctsmim 1 rw "nUARTCTS modem interrupt mask";
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rimim 1 rw "nUARTRI modem interrupt mask";
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};
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register RIS addr (base, 0x3c) "Raw Interrupt Status" {
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_ 21;
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oeris 1 ro "Overrun error interrupt status";
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beris 1 ro "Break error interrupt status";
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peris 1 ro "Parity error interrupt status";
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feris 1 ro "Framing error interrupt status";
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rtris 1 ro "Receive timeout interrupt status";
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txris 1 ro "Transmit interrupt status";
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rxris 1 ro "Receive interrupt status";
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dsrrmis 1 ro "nUARTDSR modem interrupt status";
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dcdrmis 1 ro "nUARTDCD modem interrupt status";
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ctsrmis 1 ro "nUARTCTS modem interrupt status";
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rirmis 1 ro "nUARTRI modem interrupt status";
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};
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register MIS addr (base, 0x40) "Masked Interrupt Status" {
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_ 21;
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oemis 1 ro "Overrun error masked interrupt status";
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bemis 1 ro "Break error masked interrupt status";
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pemis 1 ro "Parity error masked interrupt status";
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femis 1 ro "Framing error masked interrupt status";
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rtmis 1 ro "Receive timeout masked interrupt status";
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txmis 1 ro "Transmit masked interrupt status";
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rxmis 1 ro "Receive masked interrupt status";
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dsrmmis 1 ro "nUARTDSR modem masked interrupt status";
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dcdmmis 1 ro "nUARTDCD modem masked interrupt status";
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ctsmmis 1 ro "nUARTCTS modem masked interrupt status";
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rimmis 1 ro "nUARTRI modem masked interrupt status";
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};
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register ICR addr (base, 0x44) "Interrupt Clear" {
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_ 21 mbz;
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oeic 1 rw1c "Overrun error interrupt clear";
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beic 1 rw1c "Break error interrupt clear";
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peic 1 rw1c "Parity error interrupt clear";
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feic 1 rw1c "Framing error interrupt clear";
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rtic 1 rw1c "Receive timeout interrupt clear";
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txic 1 rw1c "Transmit interrupt clear";
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rxic 1 rw1c "Receive interrupt clear";
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dsrmic 1 rw1c "nUARTDSR modem interrupt clear";
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dcdmic 1 rw1c "nUARTDCD modem interrupt clear";
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ctsmic 1 rw1c "nUARTCTS modem interrupt clear";
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rimic 1 rw1c "nUARTRI modem interrupt clear";
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};
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register DMACR addr (base, 0x48) "DMA Control" {
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_ 29;
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dmaonerr 1 rw "DMA on error";
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txdmae 1 rw "Transmit DMA enable";
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rxdmae 1 rw "Receive DMA enable";
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};
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/*
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* Test registers: only used for integration testing
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*/
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register TCR addr (base, 0x80) "Test Control" {
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_ 29;
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sirtest 1 rw "SIR test enable";
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testfifo 1 rw "Test FIFO enable";
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iten 1 rw "Integration test enable";
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};
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register ITIP addr (base, 0x84) "Integration Test Input" {
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_ 24;
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txdmaclr 1 rw "Value to drive UARTTXDMACLR";
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rxdmaclr 1 rw "Value to drive UARTRXDMACLR";
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nuartpri 1 ro "nUARTPRI primary input";
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nuartdcd 1 ro "nUARTDCD primary input";
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nuartcts 1 ro "nUARTCTS primary input";
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nuartdsr 1 ro "nUARTDSR primary input";
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sirin 1 ro "SIRIN primary input";
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uartrxd 1 ro "UARTRXD primary input";
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};
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register ITOP addr (base, 0x88) "Integration Test Output" {
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_ 16;
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ttxdmasreq 1 rw "Intra-chip output UARTTXDMASREQ";
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ttxdmabreq 1 rw "Intra-chip output UARTTXDMABREQ";
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trxdmasreq 1 rw "Intra-chip output UARTRXDMASREQ";
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trxdmabreq 1 rw "Intra-chip output UARTDMABREQ";
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tmsintr 1 rw "Intra-chip output UARTMSINTR";
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trxintr 1 rw "Intra-chip output UARTRXINTR";
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ttxintr 1 rw "Intra-chip output UARTTXINTR";
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trtintr 1 rw "Intra-chip output UARTRTINTR";
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teintr 1 rw "Intra-chip output UARTEINTR";
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tintr 1 rw "Intra-chip output UARTINTR";
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nuartout2 1 ro "Primary output nUARTOut2";
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nuartout1 1 ro "Primary output nUARTOut1";
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nuartrts 1 ro "Primary output nUARTRTS";
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nuartdtr 1 ro "Primary output nUARTDTR";
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nsirout 1 ro "Primary output nSIROUT";
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uarttxd 1 ro "Primary output UARTTXD";
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};
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register TDR addr (base, 0x8c) "Test Data" {
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_ 21;
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data 11 rw "Data written to rx / read from tx FIFO";
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};
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/*
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* Identification registers
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*/
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register PeriphID0 ro addr (base, 0xFE0) "Peripheral ID 0" {
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_ 24 mbz;
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partnumber0 8 "Should be 0x11";
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};
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register PeriphID1 ro addr (base, 0xFE4) "Peripheral ID 1" {
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_ 24 mbz;
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designer0 4 "Should be 0x1";
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partnumber1 4 "Should be 0x0";
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};
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register PeriphID2 ro addr (base, 0xFE8) "Peripheral ID 2" {
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_ 24 mbz;
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revision 4 "Revision of the UART";
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designer1 4 "Should be 0x4";
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};
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register PeriphID3 ro addr (base, 0xFEC) "Peripheral ID 3" {
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_ 24 mbz;
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configuration 8 "Should be 0x0";
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};
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regarray CdellID addr (base, 0xFF0) [ 4 ] "Cell ID (should be 0xb105f00d)" {
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_ 24 mbz;
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id 8 "PrimeCell identification registers";
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};
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};
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