38 lines
989 B
Plaintext
38 lines
989 B
Plaintext
/*
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* Copyright (c) 2018, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* pci_msix_cap.dev
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*
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* DESCRIPTION: PCI MSI-X Capability
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*
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* Source: Section 6.8.2. in PCI Local Bus Specification
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*/
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device pci_msix_cap lsbfirst ( addr base ) "PCI MSI-X Capability" {
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// 6.8.2.(1-3)
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register hdr rw addr( base, 0x00 ) "Capabilities Header" {
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id 8 "Capability ID";
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next 8 "Next Pointer";
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tblsize 11 "Message Control - Table Size";
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res 4 "reserved";
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en 1 "MSI-X enable";
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};
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regtype location "Location" {
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bir 3 "Base Address Register Index";
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offset 29 "Offset";
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};
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register tbl ro addr(base, 0x4) "Table Location" type(location);
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register pba ro addr(base, 0x8) "Table Location" type(location);
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};
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