177 lines
5.8 KiB
Plaintext
177 lines
5.8 KiB
Plaintext
/*
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* Copyright (c) 2008, 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* pci_hdr0.dev
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*
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* DESCRIPTION: PCI Type 0 Configuration header
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*
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*/
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device pci_hdr0_mem msbfirst ( addr base ) "PCI Type 0 Configuration" {
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register vendor_id rw addr( base, 0x00 ) "Vendor ID" type(uint16);
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register device_id rw addr( base, 0x02 ) "Device ID" type(uint16);
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register command rw addr( base, 0x04 ) "Command" {
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_ 5;
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int_dis 1 rw "Interrupt disable";
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back2back 1 ro "Fast back-to-back enable";
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serr 1 rw "SERR# enable";
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stepping 1 ro "IDSEL stepping/wait cycle control";
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parity 1 rw "Parity error response";
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vga_snoop 1 ro "VGA palette snoop enable";
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mem_inval 1 ro "Memory write and invalidate enable";
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special 1 ro "Special cycles";
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master 1 rw "Bus master";
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mem_space 1 rw "Memory space enable";
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io_space 1 rw "I/O space enable";
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};
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register status addr( base, 0x06 ) "Status" {
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parity_err 1 rwc "Detected parity error";
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system_err 1 rwc "Signalled system error";
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rx_m_abrt 1 rwc "Received master abort";
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rx_t_abrt 1 rwc "Received target abort";
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sig_t_abrt 1 rwc "Signalled target abort";
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devsel 2 ro "DEVSEL timing";
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md_parity 1 rwc "Master data parity error";
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back2back 1 ro "Fast Back-to-Back enable";
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udf 1 ro "UDF supported";
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m66 1 ro "66MHz capable";
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caplist 1 ro "Capabilities list";
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intstat 1 ro "Interrupt status";
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_ 3;
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};
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//
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// Revision ID and Class code fall in the same 32-bit space. We
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// allow access to the Revision ID as an 8-bit value, and the Class
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// Code as a 32-bit value with the bottom 8 bits reserved, but we
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// could I suppose combine them all into one register.
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//
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register rev_id ro addr( base, 0x08 ) "Revision ID" type(uint8);
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constants classcode "Class code" {
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old = 0x00 "Pre-2.0 PCI device";
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mass = 0x01 "Mass storage controller";
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network = 0x02 "Network controller";
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display = 0x03 "Display controller";
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multimedia = 0x04 "Multimedia device";
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memory = 0x05 "Memory controller";
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bridge = 0x06 "Bridge device";
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simple = 0x07 "Simple communications controller";
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base = 0x08 "Base system peripherals";
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input = 0x09 "Input device";
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docking = 0x0a "Docking station";
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processor = 0x0b "Processor";
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serial = 0x0c "Serial bus controller";
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wireless = 0x0d "Wireless controller";
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intelligent = 0x0e "Intelligent I/O controller";
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satellite = 0x0f "Satellite communications controller";
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crypt = 0x10 "Encryption/decryption device";
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acquisition = 0x11 "Data acquisition controller";
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misc = 0xff "Miscellaneous";
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};
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register class_code rw also addr( base, 0x08 ) "Class code" {
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clss 8 type(classcode) "Class code";
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subclss 8 "Subclass code";
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prog_if 8 "Programming intf";
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_ 8;
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};
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register cache_sz rw addr( base, 0x0c ) "Cache line size" type(uint8);
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register latency rw addr( base, 0x0d ) "Master latency timer" type(uint8);
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//
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// Important stuff: whether this is actually a Type-0 header at
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// all. This is currently duplicated into the Type-1 definition -
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// when Mackerel gets a module system we can break this out into
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// other files.
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//
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constants hdrtype "Configuration header types" {
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nonbridge = 0 "non-bridge function";
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pci2pci = 1 "PCI-to-PCI bridge";
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cardbus = 2 "CardBus bridge";
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};
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register hdr_type ro addr( base, 0x0e ) "Header type" {
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multi 1 "Multifunction device";
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fmt 7 type(hdrtype) "Configuration header format";
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};
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register bist addr( base, 0x0f ) "Built-in self-test" {
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cap 1 ro "BIST capable";
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start 1 rw "Start BIST";
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_ 2;
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comp 4 ro "Completion code";
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};
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//
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// Base-Address registers. These are problematic for Mackerel,
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// since you don't know exactly what the register is (32, 64, or IO)
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// until you read it. And only then do you know where the next one
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// might be. This is beyond Mackerel, and in all honesty probably
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// should stay that way.
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//
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// As a compromise we define register types for each BAR, and give
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// the BAR block as simply a set of 6 32-bit registers. PCI
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// enumeration code can do the rest.
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//
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constants bardecoder "BAR decoder type" {
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bar_32bit = 0b00 "32-bit decoder";
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bar_64bit = 0b10 "64-bit decoder";
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};
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regtype bar32 "32-bit memory base address" {
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base 25 rw "Base address";
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_ 3;
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prefetch 1 ro "Prefetchable";
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tpe 2 ro type(bardecoder) "Memory decoder type";
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space 1 ro "Memory space indicator";
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};
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regtype bar64 "64-bit memory base address" {
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base 57 rw "Base address";
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_ 3;
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prefetch 1 ro "Prefetchable";
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tpe 2 ro type(bardecoder) "Memory decoder type";
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space 1 ro "Memory space indicator";
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};
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regtype bario "I/O space base address" {
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base 30 rw "Base address";
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_ 1;
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space 1 ro "I/O space indicator";
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};
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regarray bars addr( base, 0x10 ) [5] "Base address registers" type(uint32);
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register cardbus ro addr(base, 0x28) "CardBus CIS ptr" type(uint32);
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register subsys_vid ro addr(base, 0x2c) "Subsystem vendor ID" type(uint16);
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register subsys_id ro addr(base, 0x2e) "Subsystem ID" type(uint16);
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register rom_base rw addr(base, 0x30) "Expansion ROM base addr" {
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base 21 "ROM Base address high bits";
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_ 10;
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enable 1 "ROM address decoder enable";
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};
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register cap_ptr ro addr(base, 0x34) "Capabilities ptr" type(uint8);
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register int_line rw addr(base, 0x3c) "Interrupt line" type(uint8);
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register int_pin ro addr(base, 0x3d) "Interrupt ping" type(uint8);
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register min_gnt ro addr(base, 0x3e) "Min Gnt" type(uint8);
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register max_lat ro addr(base, 0x3f) "Max Lat" type(uint8);
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};
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