72 lines
3.7 KiB
Plaintext
72 lines
3.7 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_hdq_1_wire.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_hdq_1_wire msbfirst ( addr base ) "" {
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register hdq_revision ro addr(base, 0x0) "This register contains the IP revision code" type(uint32);
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register hdq_tx_data addr(base, 0x4) "This register contains the data to be transmitted." {
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_ 24 mbz;
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tx_data 8 rw "Transmit data (used in both HDQ and 1-Wire modes)";
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};
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register hdq_rx_data addr(base, 0x8) "This register contains the data to be received." {
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_ 24 mbz;
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rx_data 8 ro "Receive data (used in both HDQ and 1-Wire modes)";
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};
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register hdq_ctrl_status addr(base, 0xC) "This register provides status information about the module." {
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_ 24 mbz;
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one_wire_single_bit 1 rw "Single-bit mode for 1-Wire0x0: Disabled 0x1: Enabled";
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interruptmask 1 rw "Interrupt masking bit0x0: Interrupts disable 0x1: Interrupts enable";
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clockenable 1 rw "Power-down mode bit0x0: Clock disable (power down)0x1: Clock enable";
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go 1 rw "Go bit. Write 1 to start the appropriate operation. Bit returns to 0 after the operation is complete.";
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presencedetect 1 ro "Slave presence indicator. Actual only just after initialization time-out. Used in 1-Wire mode. Read-only flag.0x0: No slave detected0x1: Slave detected";
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initialization 1 rw "Write 1 to send initialization pulse. Bit returns to 0 after pulse is sent.";
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dir 1 rw "DIR bit, determines if next command is read or write0x0: Write 0x1: Read";
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mode 1 rw "Mode selection bit0x0: HDQ mode 0x1: 1-Wire mode";
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};
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register hdq_int_status addr(base, 0x10) "This register controls interrupts status" {
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_ 29 mbz;
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txcomplete 1 ro "TX-complete interrupt flag.Set to 1 if cause of interrupt. Set to 0 when register read.";
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rxcomplete 1 ro "Read-complete interrupt flag.Set to 1 if cause of interrupt. Set to 0 when register read.";
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timeout 1 ro "Presence detect/timeout interrupt flag.In 1-Wire mode, set to 1 if slave's presence detected. In HDQ mode, set to 1 if timeout on read occurs. Set to 0 when register read.";
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};
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register hdq_sysconfig addr(base, 0x14) "This register controls various bits" {
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_ 30 mbz;
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softreset 1 rw "Start soft reset sequence.0x0: Disabled 0x1: Enabled";
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autoidle 1 rw "Interconnect idle.0x0: Module clock is free-running. 0x1: Module is in power saving mode: Clock is running only when module is accessed or inside logic is in function to process events.";
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};
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register hdq_sysstatus addr(base, 0x18) "This register monitors the reset sequence." {
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_ 31 mbz;
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resetdone 1 ro "Reset monitoring.0x0: The module is currently performing its reset. When the module is in power-down mode, set to 0 to indicate this fact. 0x1: The module has finished its reset.";
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};
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}; |