245 lines
8.4 KiB
Plaintext
245 lines
8.4 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* lpuart.dev
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*
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* DESCRIPTION: Low Power UART
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*
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* This is derived from:
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*
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* i.MX 8DualXPlus Appliacations Processor Reference Manual, revision D, NXP
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* Pages 2255 - 2298
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* (IMX8DQXPRM.pdf)
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*
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*/
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device lpuart msbfirst (addr base) "LPUART" {
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constants feature "feature set number" {
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standard = 0b01 "Standard feature set";
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irda = 0b11 "Standard feature set with MODEM/IrDA support";
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};
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constants trgsel "trigger select" {
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disabled = 0b00 "Input trigger is disabled.";
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rx = 0b01 "Input trigger is used instead of RX pin input.";
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ctsb = 0b10 "Input trigger is used instead of CTS_B pin input.`";
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modrx = 0b11 "Input trigger is used to modulate TX pin output.";
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};
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constants osr "oversampling ratio" {
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default = 0b00000 "Writing 0 to this field will result in an oversampling ratio of 16.";
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ratio4 = 0b00011 "Oversampling ratio of 4, requires BOTHEDGE to be set.";
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ratio5 = 0b00100 "Oversampling ratio of 5, requires BOTHEDGE to be set.";
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ratio6 = 0b00101 "Oversampling ratio of 6, requires BOTHEDGE to be set.";
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ratio7 = 0b00110 "Oversampling ratio of 7, requires BOTHEDGE to be set.";
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ratio8 = 0b00111 "Oversampling ratio of 8.";
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ratio9 = 0b01000 "Oversampling ratio of 9.";
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ratio10 = 0b01001 "Oversampling ratio of 10.";
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ratio11 = 0b01010 "Oversampling ratio of 11.";
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ratio12 = 0b01011 "Oversampling ratio of 12.";
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ratio13 = 0b01100 "Oversampling ratio of 13.";
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ratio14 = 0b01101 "Oversampling ratio of 14.";
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ratio15 = 0b01110 "Oversampling ratio of 15.";
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ratio16 = 0b01111 "Oversampling ratio of 16.";
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ratio17 = 0b10000 "Oversampling ratio of 17.";
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ratio18 = 0b10001 "Oversampling ratio of 18.";
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ratio19 = 0b10010 "Oversampling ratio of 19.";
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ratio20 = 0b10011 "Oversampling ratio of 20.";
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ratio21 = 0b10100 "Oversampling ratio of 21.";
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ratio22 = 0b10101 "Oversampling ratio of 22.";
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ratio23 = 0b10110 "Oversampling ratio of 23.";
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ratio24 = 0b10111 "Oversampling ratio of 24.";
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ratio25 = 0b11000 "Oversampling ratio of 25.";
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ratio26 = 0b11001 "Oversampling ratio of 26.";
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ratio27 = 0b11010 "Oversampling ratio of 27.";
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ratio28 = 0b11011 "Oversampling ratio of 28.";
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ratio29 = 0b11100 "Oversampling ratio of 29.";
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ratio30 = 0b11101 "Oversampling ratio of 30.";
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ratio31 = 0b11110 "Oversampling ratio of 31.";
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ratio32 = 0b11111 "Oversampling ratio of 32.";
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};
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register verid ro addr(base, 0x0) "Version ID Register" {
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major 8 "Major Version Number";
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minor 8 "Minor Version Number";
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feature 16 type(feature) "Feature Identification Number";
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};
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register param ro addr(base, 0x4) "Parameter Register" {
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_ 16;
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rxfifo 8 "Receive FIFO size (2^RXFIFO)";
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txfifo 8 "Transmit FIFO size (2^FIFO)";
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};
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register global ro addr(base, 0x8) "LPUART Global Register" {
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_ 30;
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rst 1 rw "Software Reset";
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_ 1;
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};
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register pincfg addr(base, 0xc) "LPUART Pin Configuration Register" {
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_ 30;
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trgsel 2 rw type(trgsel) "Trigger select";
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};
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register baud addr(base, 0x10) "LPUART Baud Rate Register" {
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maen1 1 "Match address mode enable 1";
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maen2 1 "Match address mode enable 2";
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m10 1 "10-bit mode select";
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osr 5 type(osr) "Oversampling ratio";
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tdmae 1 "Transmitter DMA Enable";
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_ 1;
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rdmae 1 "Receiver Full DMA Enable";
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ridmae 1 "Receiver idle DMA Enable";
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matcfg 2 "Match Configuration";
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bothedge 1 "Both Edge Sampling";
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resynccdis 1 "Resynchronization Disable";
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lbkdie 1 "LIN Break Detect Interrupt Enable";
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rxedgie 1 "RX Input Active Edge Interrupt Enable";
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sbns 1 "Stop Bit Number Select";
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sbr 13 "Baud Rate Modulo Divisor";
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};
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register stat addr(base, 0x14) "LPUART Status Register" {
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lbkdif 1 rw1c "LIN Break Detect Interrupt flag";
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rxedgif 1 rw1c "RX Pin Active Edge Interrupt Flag";
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msbf 1 "MSB first";
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rxinv 1 "Receive Data Inversion";
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rwuid 1 "Whether idle char sets IDLE bit.";
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brk13 1 "Break Character Generation Length";
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lbkde 1 "LIN Break Detection Enable";
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raf 1 ro "Receiver Active Flag";
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tdre 1 ro "Transmit Data Register Empty Flag";
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tc 1 ro "Transmit Complete Flag";
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rdrf 1 ro "Receive Data Register Full Flag";
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idle 1 rw1c "Idle Line Flag";
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or 1 rw1c "Receiver Overrun Flag";
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nf 1 rw1c "Noise Flag";
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fe 1 rw1c "Framing Error Flag";
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pf 1 rw1c "Parity Error Flag";
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ma1f 1 rw1c "Match 1 Flag";
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ma2f 1 rw1c "Match 2 Flag";
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_ 14;
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};
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register ctrl addr(base, 0x18) "LPUART Control Register" {
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r8t9 1 "Receive Bit 8 / Transmit Bit 9";
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r9t8 1 "Receive Bit 9 / Transmit Bit 8";
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txdir 1 "TX Pin Direction Single-Wire Mode";
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txinv 1 "Transmit Data Inversion";
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orie 1 "Overrrun Interrupt Enable";
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neie 1 "Noise Error Interrupt Enable";
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feie 1 "Framing Error Interrupt Enable";
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peie 1 "Parity Error Interrupt Enable";
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tie 1 "Transmit Interrupt Enable";
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tcie 1 "Transmission Complete Interrupt Enable";
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rie 1 "Receiver Interrupt Enable";
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iue 1 "Idle Line Interrupt Enable";
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te 1 "Transmitter Enable";
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re 1 "Receiver Enable";
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rwu 1 "Receiver Wakeup Control";
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sbk 1 "Send Break";
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ma1ie 1 "Match 1 Interrupt Enable";
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ma2ie 1 "Match 2 Interrupt Enable";
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_ 2;
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m7 1 "7-Bit Mode Select";
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idlecfg 3 "Idle Configuration (2^IDLECFG idle characters before IDLE flag set)";
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loops 1 "Loop Mode Select";
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dozeen 1 "Doze Enable";
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rsrc 1 "Receiver Source Select";
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m 1 "9-Bit or 8-Bit Mode Select";
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wake 1 "Receiver Wakeup Method Select";
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ilt 1 "Idle Line Type Select";
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pe 1 "Parity Enable";
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pt 1 "Parity Type";
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};
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/*
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* Data register is actually two registers for RX/TX
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* To prevent Mackerel from generating code for reading
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* things via the TX register and therefore clearing the RX
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* register we declare the readonly fields as mbz in the TX
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* register.
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*/
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register rxdata ro addr(base, 0x1c) "LPUART Receive Data Register" {
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_ 16;
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noisy 1 "Whether received with noise.";
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paritye 1 "Whether received with parity error.";
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fre 1 "Whether received with frame error";
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rxempt 1 "Receive Buffer Empty";
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idline 1 "Idle Line";
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_ 1;
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buf 10 "Data buffer";
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};
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register txdata wo also addr(base, 0x1c) "LPUART Transmit Data Register" {
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_ 16 mbz;
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_ 1 mbz;
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_ 1 mbz;
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tsc 1 "Transmit Special Character";
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_ 1 mbz;
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_ 1 mbz;
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_ 1 mbz;
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buf 10 "Data buffer";
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};
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register match addr(base, 0x20) "LPUART Match Address Register" {
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_ 6;
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ma2 10 "Match Address 2";
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_ 6;
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ma1 10 "Match Address 1";
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};
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register modir addr(base, 0x24) "LPUART Modem IrDA Register" {
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_ 13;
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iren 1 "Infrared enable";
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tnp 2 "Transmitter narrow pulse";
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_ 2;
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rtswater 6 "Receive RTS Configuration";
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_ 2;
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txctssrc 1 "Transmit CTS Source";
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txctsc 1 "Transmit CTS Configuration";
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rxrtse 1 "Receiver request-to-send enable";
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txrtspol 1 "Transmitter request-to-send polarity";
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txrtse 1 "Transmitter request-to-send enable";
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txctse 1 "Transmitter clear-to-send enable";
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};
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register fifo addr(base, 0x28) "LPUART FIFO Register" {
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_ 8;
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txempt 1 ro "Transmit Buffer/FIFO Empty";
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rxempt 1 ro "Receive Buffer/FIFO Empty";
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_ 4;
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txof 1 rw1c "Trasnmitter Buffer Overflow Flag";
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rxuf 1 rw1c "Receiver Buffer Underflow Flag";
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txflush 1 wo "Transmit FIFO/Buffer Flush";
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rxflush 1 wo "Receive FIFO/Buffer Flush";
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_ 1;
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rxiden 3 "Receiver Idle Empty Enable";
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txofe 1 "Transmit FIFO Overflow Interrupt Enable";
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rxufe 1 "Receive FIFO Underflow Interrupt Enable";
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txfe 1 "Transmit FIFO Enable";
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txfifosize 3 ro "Transmit FIFO Buffer Depth";
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rxfe 1 "Receive FIFO Enable";
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rxfifosize 3 ro "Receive FIFO Buffer Depth";
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};
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register water addr(base, 0x2c) "LPUART Watemark Register" {
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_ 1;
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rxcount 7 ro "Receive Counter";
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_ 2;
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rxwater 6 "Receiver Watermark";
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_ 1;
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txcount 7 ro "Transmit Counter";
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_ 2;
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txwater 6 "Transmit Watermark";
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};
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};
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