89 lines
3.1 KiB
Plaintext
89 lines
3.1 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* lpc_timer.dev
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*
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* DESCRIPTION: Legacy timer registers on the LPC (low pin count, or
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* legacy PC) bridge function of a typical Intel IHC
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* (Southbridge).
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*
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* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
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* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
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*/
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device lpc_timer (io base) "LPC Timer" {
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//
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// Section 21.3: Timer I/O registers
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//
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constants cnt_mode "Counter mode" {
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oseoc = 0b000 "Out signal on end of count (mode 0)";
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hr1s = 0b001 "Hardware retriggerable one-shot (mode 1)";
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rtgen = 0b010 "Rate generator (mode 2)";
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rtgen_ = 0b110 "Rate generator (mode 2)";
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sqwav = 0b011 "Square wave output (mode 3)";
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sqwav_ = 0b111 "Square wave output (mode 3)";
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swstr = 0b100 "Software triggered strobe (mode 4)";
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hwstr = 0b101 "Hardware triggered strobe (mode 5)";
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};
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constants timer_rwsel "Read/write select" {
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clc = 0b00 "Counter latch cmd";
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lsb = 0b01 "R/w least sig. byte";
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msb = 0b10 "R/w most sig. byte";
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lmsb = 0b11 "R/w lsb then msb";
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};
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constants timer_cntsel "Counter select" {
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c0 = 0b00 "Counter 0";
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c1 = 0b01 "Counter 1";
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c2 = 0b10 "Counter 2";
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rb = 0b11 "Read back cmd";
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};
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register tcw wo io( base, 0x3 ) "Timer Control Word" {
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bcd 1 "Binary coded decimal select";
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mode 3 type(cnt_mode) "Counter mode";
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rwsel 2 type(timer_rwsel) "Read/write select";
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select 2 type(timer_cntsel) "Counter select";
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};
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register rdbk_cmd wo also io( base, 0x3 ) "Read back command" {
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_ 1 mbz;
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c0 1 "Counter 0 select";
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c1 1 "Counter 1 select";
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c2 1 "Counter 2 select";
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stat 1 "Latch status of selected counters";
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count 1 "Latch count of selected counters";
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_ 2 mb1;
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};
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register ltch_cmd wo also io( base, 0x3 ) "Counter latch command" {
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_ 6 mbz;
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select 2 type(timer_cntsel) "Counter select";
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};
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regtype sbyte_fmt "Interval timer status byte format" {
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bcd 1 "Binary coded decimal select";
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mode 3 type(cnt_mode) "Counter mode";
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rwsel 2 type(timer_rwsel) "Read/write select";
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cnt_stat 1 "Count register status";
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cnt_out 1 "Counter OUT pin status";
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};
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register sbyte_fmt0 ro io( base, 0x0 ) "Int. timer 0 status format" type(sbyte_fmt);
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register sbyte_fmt1 ro io( base, 0x1 ) "Int. timer 1 status format" type(sbyte_fmt);
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register sbyte_fmt2 ro io( base, 0x2 ) "Int. timer 2 status format" type(sbyte_fmt);
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register cntacc0 rw also io( base, 0x0 ) "Counter 0 access" type(uint8);
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register cntacc1 rw also io( base, 0x1 ) "Counter 1 access" type(uint8);
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register cntacc2 rw also io( base, 0x2 ) "Counter 2 access" type(uint8);
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};
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