115 lines
3.2 KiB
Plaintext
115 lines
3.2 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* lpc_rtc.dev
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*
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* DESCRIPTION: Legacy real-time clock registers on the LPC (low pin count, or
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* legacy PC) bridge function of a typical Intel IHC
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* (Southbridge).
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*
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* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
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* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
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*
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*/
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device lpc_rtc (io base) "LPC Real-Time Clock and CMOS RAM" {
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// 21.6
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register ndx rw io(base, 0x70) "Standard index" type(uint8);
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register target rw io(base, 0x71) "Standard target" type(uint8);
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register endx rw io(base, 0x72) "Extended index" type(uint8);
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register etarget rw io(base, 0x73) "Extended target" type(uint8);
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// 21.6.2
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constants sndx "Standard index values" {
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seconds = 0x0 "Seconds";
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al_seconds = 0x1 "Seconds alarm";
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minutes = 0x2 "Minutes";
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al_minutes = 0x3 "Minutes Alarm";
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hours = 0x4 "Hours";
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al_hours = 0x5 "Hours Alarm";
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weekday = 0x6 "Day of Week";
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date = 0x7 "Day of Month";
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month = 0x8 "Month";
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year = 0x9 "Year";
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rega = 0xa "Register A";
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regb = 0xb "Register B";
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regc = 0xc "Register C";
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regd = 0xd "Register D";
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};
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// 21.6.2.1
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constants dcs "Division chain select" {
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normal = 0b010 "Normal operation";
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divreset = 0b110 "Divider reset";
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divreset2 = 0b111 "Divider reset";
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bypass15 = 0b101 "Bypass 15 stages";
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bypass10 = 0b100 "Bypass 10 stages";
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bypass5 = 0b011 "Bypass 5 stages";
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};
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constants rate "Rate select" {
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never = 0b0000 "Interrupt never toggles";
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ms3_90625_ = 0b0001 "3.90625 ms (duplicate)";
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ms7_8125_ = 0b0010 "7.8125 ms (duplicate)";
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us122_070 = 0b0011 "122.070 us";
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us244_141 = 0b0100 "244.141 us";
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us488_281 = 0b0101 "488.281 us";
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us976_5625 = 0b0110 "976.5625 us";
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ms1_953125 = 0b0111 "1.953125 ms";
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ms3_906251 = 0b1000 "3.906251 ms";
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ms7_8125 = 0b1001 "7.8125 ms";
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ms15_625 = 0b1010 "15.625 ms";
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ms31_25 = 0b1011 "31.25 ms";
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ms62_5 = 0b1100 "62.5 ms";
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ms125 = 0b1101 "125 ms";
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ms250 = 0b1110 "250 ms";
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ms500 = 0b1111 "500 ms";
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};
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register rega rw also io(base, 0x71) "Register A" {
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rs 4 type(rate) "Rate select";
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dv 3 type(dcs) "Divisioin chain select";
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uip 1 "Update in progress";
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};
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// 26.6.2.2
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register regb rw also io(base, 0x71) "General configuration" {
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dse 1 "Daylight savings enable";
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hourform 1 "Hour format";
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dm 1 "Data mode (BCD/binary)";
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sqwe 1 "Square wave enable";
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uie 1 "Update-ended interrupt enable";
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aie 1 "Alarm interrupt enable";
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pie 1 "Periodic interrupt enable";
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set 1 "Update cycle inhibit";
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};
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// 26.6.2.3
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register regc ro also io(base, 0x71) "Flag register C" {
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_ 4;
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uf 1 "Update-ended";
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af 1 "Alarm";
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pf 1 "Periodic interrupt";
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irqf 1 "Interrupt request flag";
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};
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// 26.6.2.4
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register regd rw also io(base, 0x71) "Flag register D" {
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al_date 6 "Date alarm";
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_ 1;
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vrt 1 mbz "Valid RAM and time";
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};
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};
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