139 lines
5.0 KiB
Plaintext
139 lines
5.0 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* lpc_pic.dev
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*
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* DESCRIPTION: Definition of the LPC (low pin count, or legacy PC)
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* bridge function of a typical Intel IHC (Southbridge).
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*
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* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
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* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
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*
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*/
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device lpc_pic lsbfirst (io base) "LPC IHC PIC function" {
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//
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// 8259 PIC registers: section 21.4
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//
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constants rrc "Register read command" {
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read_irq = 0b10 "Read IRQ register";
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read_is = 0b11 "Read IS register";
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};
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constants rsleoi "Rotate and EOI codes" {
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raeoic = 0b000 "Rotate in auto EOI mode (clear)";
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eoi = 0b001 "Non-specific EOI command";
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seoi = 0b011 "Specific EOI command";
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raeois = 0b100 "Rotate in auto EOI mode (set)";
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reoi = 0b101 "Rotate on non-specific EOI command";
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sp = 0b110 "Set priority command";
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rseoi = 0b111 "Rotate on specific EOI command";
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};
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regtype icw1 "Initialization Command Word 1" {
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_ 1 mb1;
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_ 1 mbz; // Specify cascade mode
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_ 1 mbz;
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ltim 1 "Edge / Level bank select (ignored)";
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_ 1 mb1;
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_ 3 mbz;
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};
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regtype icw2 "Initialization Command Word 2" {
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req_level 3 "Interrupt request level";
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base 5 "Interrupt vector base address";
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};
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regtype pic_master_icw3 "Master Controller Initialization Command Word 3" {
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_ 2 mbz;
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cascade 1 "Cascaded PIC IRQ connection";
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_ 5 mbz;
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};
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regtype pic_slave_icw3 "Slave Controller Initialization Command Word 3" {
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slave_id 3 "Slave Identification Code";
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_ 5 mbz;
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};
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regtype icw4 "Initialization Command Word 4" {
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_ 1 mb1;
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aeoi 1 "Automatic End of Interrupt";
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_ 1 mbz;
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_ 1 mbz;
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sfnm 1 "Special fully nested mode";
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_ 3 mbz;
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};
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/*
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regtype ocw1 "Operational Control Word 1 (Interrupt Mask)" {
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irq_mask 8 type(uint8) "Interrupt request mask";
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};
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*/
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regtype ocw2 "Operational Control Word 2" {
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level 3 "Interrupt level select";
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_ 2 mbz;
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rsleoi 3 type(rsleoi) "Rotate and EOI Codes";
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};
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regtype ocw3 "Operational Control Word 3" {
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rrc 2 type(rrc) "Register read command";
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pmc 1 "Poll mode command";
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_ 1 mb1;
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_ 1 mbz;
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esmm 1 "Enable special mask mode";
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smm 1 "Special mask mode";
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_ 1 mbz;
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};
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regtype pic_master_trigger "Master Controller Edge/Level Triggered" {
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_ 3 mbz;
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irq3_ecl 1 "IRQ3 ECL";
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irq4_ecl 1 "IRQ4 ECL";
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irq5_ecl 1 "IRQ5 ECL";
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irq6_ecl 1 "IRQ6 ECL";
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irq7_ecl 1 "IRQ7 ECL";
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};
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regtype pic_slave_trigger "Slave Controller Edge/Level Triggered" {
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_ 1 mbz;
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irq9_ecl 1 "IRQ9 ECL";
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irq10_ecl 1 "IRQ10 ECL";
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irq11_ecl 1 "IRQ11 ECL";
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irq12_ecl 1 "IRQ12 ECL";
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_ 1 mbz;
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irq14_ecl 1 "IRQ14 ECL";
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irq15_ecl 1 "IRQ15 ECL";
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};
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register master_icw1 wo io( base, 0x20 ) "Master PIC Initialization Command Word 1" type(icw1);
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register master_ocw2 wo also io( base, 0x20 ) "Master PIC Op Ctrl Word 2" type(ocw2);
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register master_ocw3 wo also io( base, 0x20 ) "Master PIC Op Ctrl Word 3" type(ocw3);
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register master_ocw3rd ro also io( base, 0x20 ) "Master PIC Op Ctrl Word 3" type(uint8);
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register master_icw2 wo io( base, 0x21 ) "Master PIC Initialization Command Word 2" type(icw2);
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register master_icw3 wo also io( base, 0x21 ) "Master PIC Initialization Command Word 3" type(pic_master_icw3);
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register master_icw4 wo also io( base, 0x21 ) "Master PIC Initialization Command Word 4" type(icw4);
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register master_ocw1 rw also io( base, 0x21 ) "Master PIC Operation Control Word 1" type(uint8);
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register slave_icw1 wo io( base, 0xa0 ) "Slave PIC Initialization Command Word 1" type(icw1);
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register slave_ocw2 wo also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 2" type(ocw2);
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register slave_ocw3 wo also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 3" type(ocw3);
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register slave_ocw3rd ro also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 3" type(uint8);
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register slave_icw2 wo io( base, 0xa1 ) "Slave PIC Initialization Command Word 2" type(icw2);
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register slave_icw3 wo also io( base, 0xa1 ) "Slave PIC Initialization Command Word 3" type(pic_slave_icw3);
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register slave_icw4 wo also io( base, 0xa1 ) "Slave PIC Initialization Command Word 4" type(icw4);
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register slave_ocw1 rw also io( base, 0xa1 ) "Slave PIC Operation Control Word 1" type(uint8);
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register master_trigger rw io( base, 0x4d0 ) "Master PIC Edge/Level Triggered" type(pic_master_trigger);
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register slave_trigger rw io( base, 0x4d1 ) "Slave PIC Edge/Level Triggered" type(pic_slave_trigger);
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};
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