27 lines
809 B
Plaintext
27 lines
809 B
Plaintext
/*
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* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* lpc_bridge.dev
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*
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* DESCRIPTION: this maps to the PCI configuration space of the LPC bridge
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* and maps currently only the RCBA register, so that we can
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* access the base of the chipset configuration which we need
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* to implement the HPET timer
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*
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*/
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device lpc_bridge msbfirst ( pci base ) "LPC bridge PCI config space" {
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register rcba rw pci( base, 0xf0 ) "RCBA" {
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baseaddr 18 "Base Address";
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_ 13;
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enable 1 "Enable";
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};
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};
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