151 lines
5.1 KiB
Plaintext
151 lines
5.1 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* netronome_uart.dev
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*
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* DESCRIPTION: Netronome Universal Asynchronous Receiver Transmitter
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* similar to 16550 UART
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*
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* This is derived from the Intel IXP2400/IXP2800 Network Processor
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* Programmer's Reference Manual (November 2003), p. 364ff
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*/
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device ixp2800_uart msbfirst ( addr base ) "Netronome UART Memory Represenation" {
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/* Bram: I cannot verify this, maybe p.365 gives hints? */
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/* ******************************************************/
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constants divisor "Baud Rate Divisor" {
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baud50 = 2304 "50 bps";
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baud75 = 1536 "75 bps";
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baud110 = 1047 "110 bps";
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baud134_5 = 857 "134.5 bps";
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baud150 = 768 "150 bps";
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baud300 = 384 "300 bps";
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baud600 = 192 "600 bps";
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baud1200 = 96 "1200 bps";
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baud1800 = 64 "1800 bps";
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baud2000 = 58 "2000 bps";
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baud2400 = 48 "2400 bps";
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baud4800 = 24 "4800 bps";
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baud7200 = 16 "7200 bps";
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baud9600 = 12 "9600 bps";
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baud19200 = 6 "19200 bps";
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baud38400 = 3 "38400 bps";
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baud57600 = 2 "57600 bps";
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baud115200 = 1 "115200 bps";
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};
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constants interrupt_source "Interrupt Source Encoded" {
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request_data = 0b01 "Transmit FIFO requests data";
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recv_data_av = 0b10 "Received Data Available";
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recv_error = 0b11 "Receive error";
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};
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constants fifo_type "FIFO Mode Enable Status" {
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no_fifo = 0b00 "No FIFO";
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fifo_enabled = 0b11 "FIFO enabled";
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};
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constants interrupt_trigger "Interrupt Trigger Level" {
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bytes01 = 0b00 "1 byte in FIFO causes interrupt";
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bytes08 = 0b01 "8 byte in FIFO causes interrupt";
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bytes16 = 0b10 "16 byte in FIFO causes interrupt";
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bytes32 = 0b11 "32 byte in FIFO causes interrupt";
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};
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constants char_len "Character Length" {
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bits5 = 0b00 "5 Bits";
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bits6 = 0b01 "6 Bits";
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bits7 = 0b10 "7 Bits";
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bits8 = 0b11 "8 Bits";
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};
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register RBR ro addr ( base, 0x0 ) "Receiver buffer" {
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_ 24 ro "Reserved";
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rbr 8 ro "Receive Buffer Register. Data byte received, least significant bit first";
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};
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register THR also addr ( base , 0x0 ) "Transmitter holding" {
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_ 24 ro "Reserved";
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thr 8 wo "Data byte transmitted, least significant bit first";
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};
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register DLRL also addr (base , 0x0) "Divisor Latch low" {
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_ 24 ro "Reserved";
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lb 8 rw "Low byte for generating baud rate";
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};
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register DLRH addr (base , 0x4) "Divisor Latch high" {
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_ 24 ro "Reserved";
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hb 8 rw "High byte for generating baud rate";
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};
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register IER also addr ( base, 0x4 ) "Interrupt enable" {
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_ 25 ro "Reserved";
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uue 1 rw "UART Unit Enable";
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nrze 1 rw "NRZ coding Enable";
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rtoie 1 rw "Receiver Time out Interrupt Enable";
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_ 1 rw "Reserved";
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rlse 1 rw "Receiver Line Status Interrupt Enable";
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tie 1 rw "Transmit Data request Interrupt Enable";
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ravie 1 rw "Receiver Data Available Interrupt Enable";
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};
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register iir addr ( base, 0x8 ) "Interrupt identification" {
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_ 24 ro "Reserved";
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FIFOES 2 ro type(fifo_type) "FIFO Mode Enable Status";
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_ 2 ro "Reserved";
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TOD 1 ro "Time Out Detected (0: No time out interrupt is pending)";
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IID 2 ro type(interrupt_source) "Interrupt Source Encoded";
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IP 1 ro "Interrupt Pending";
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};
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register fcr rw also addr ( base, 0x8 ) "FIFO control" {
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_ 24 ro "Reserved";
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ITL 2 wo type(interrupt_trigger) "Interrupt Trigger Level";
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_ 3 ro "Reserved";
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RESETTF 1 wo "Reset transmitter FIFO";
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RESETRF 1 wo "Reset Receiver FIFO";
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TRFIFOE 1 wo "Transmit and Receive FIFO Enable";
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};
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register LCR addr ( base, 0xC ) "Line control" {
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_ 24 ro "Reserved";
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dlab 1 rw "Divisor latch access";
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sb 1 rw "Set break";
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stkyp 1 rw "Stick parity";
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eps 1 rw "Even parity select";
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pen 1 rw "Parity enable";
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stb 1 rw "Number of stop bits";
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wls 2 rw type(char_len) "Word length select";
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};
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register LSR addr ( base, 0x14 ) "Line status" {
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_ 24 ro "Reserved";
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fifoe 1 ro "FIFO Error Status ";
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temt 1 ro "Transmitter empty";
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tdrq 1 ro "Transmit Data Request";
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bi 1 ro "Break interrupt";
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fe 1 ro "Framing error";
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pe 1 ro "Parity error";
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oe 1 ro "Overrun error";
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dr 1 ro "Data ready";
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};
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register spr addr ( base, 0x1c ) "Scratchpad register" {
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_ 24 ro "Reserved";
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scratch 8 rw "No effect on UART functionality";
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};
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};
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