86 lines
3.6 KiB
Plaintext
86 lines
3.6 KiB
Plaintext
/*
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* Copyright (c) 2007 - 2018, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* hpet.dev
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*
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* DESCRIPTION: Intel 631xESB/632xESB I/O Controller Hub --
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* High-Precision Event Timer Registers
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*
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* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
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* Datasheet", chapter 26, "High-Precision Event Timer Registers".
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* See also, Intel's "IA-PC HPET (High Precision Event Timers)
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* Specification", Revision 1.0a, October 2004.
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*/
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// device device_name leastSignBitFirst
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device hpet lsbfirst ( addr base ) "High-Precision Event Timer" {
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// 26.1.1
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register gcap_id ro addr(base, 0x0) "General Capabilities and Identification" {
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rev_id 8 "Revision Identification";
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num_tim_cap 5 "Number of Timers";
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count_size_cap 1 "Counter Size";
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_ 1 mbz;
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leg_rt_cap 1 "Legacy Replacement Rout Capable";
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vendor_id_cap 16 "Vendor ID";
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counter_clk_per_cap 32 "Main Counter Tick Period";
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};
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// 26.1.2 register name attribute space(, ) "description"
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register gen_conf rw addr(base, 0x10) "General Configuration" {
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enable_cnf 1 "Overall Enable";
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leg_rt_cnf 1 "Legacy Replacement Rout";
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_ 62 mbz;
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};
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// 26.1.3
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register gintr_sta rw addr(base, 0x20) "General Interrupt Status" {
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t00_int_sts 1 "Timer 0 interrupt active";
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t01_int_sts 1 "Timer 1 interrupt active";
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t02_int_sts 1 "Timer 2 interrupt active";
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_ 61 mbz;
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};
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// 26.1.4
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register main_cnt rw addr(base, 0xf0) "Main Counter Value" type(uint64);
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// 26.1.5
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regtype tim_conf "Timer Configuration and Capabilities" {
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_ 1 mbz;
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timer_int_type_cnf 1 "Timer Interrupt Type (0:edge-triggered , 1:level-triggered)";
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timer_int_enb_cnf 1 "Timer Interrupt Enable";
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timer_type_cnf 1 "Timer Type (0: non-periodic , 1:periodic)";
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timer_per_int_cap 1 "Periodic Interrupt Capability";
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timer_size_cap 1 "Timer Size (0:32 bits , 1:64 bits)";
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timer_val_set_cnf 1 "Timer Value Set (for periodic mode)";
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_ 1 mbz;
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timer_32mode_cnf 1 "Timer 32-bit mode (1 so that 64 behaves as 32)";
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timer_int_rout_cnf 5 "Interrupt Route (indicates routing to I/O apic)";
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timer_fsb_enb_cnf 1 "FSB Interrupt Enable";
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timer_fsb_int_delv_cap 1 "FSB Interrupt Delivery (1: FSB is supported)";
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_ 16 mbz;
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timer_int_rout_cap 32 "Interrupt Routing Capability (To which interrupts can the I/O Apic be routed)";
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};
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regtype tim_fsb_int_route "Timer FSB Interrupt Route"{
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timer_fsb_int_val 32 "Timer FSB Interrupt Value";
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timer_fsb_int_addr 32 "Timer FSB Interrupt Address";
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};
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regarray timers_config_reg rw addr(base,0x100) [32 ; 0x20]
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"Timer N Configuration Register" type(tim_conf);
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regarray timers_comparator_reg rw addr(base,0x108) [32 ; 0x20]
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"Timer N Comparator Value Register" type(uint64);
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regarray timers_fsb_int_route_reg rw addr(base,0x110) [32 ; 0x20]
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"Timer N FSB Interrupt Route" type(tim_fsb_int_route);
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};
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