470 lines
16 KiB
Plaintext
470 lines
16 KiB
Plaintext
/*
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* Copyright (c) 2009, 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* ehci.dev
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*
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* DESCRIPTION: Enhanced Host Controller Interface description
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*
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* Numbers in comments refer to the Intel Enhanced Host Controller
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* Interface Specification for Universal Serial Bus, March 12, 2002,
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* Revision: 1.0
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*/
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device ehci msbfirst (addr cap, addr op) "EHCI USB Controller" {
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/*
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* Section 2.2
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* Host controller capabilty registers
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*/
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// 2.2.1
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// The correct value for 'op' is actually 'cap' plus this number.
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register caplength ro addr(cap, 0x00) "Capability Registers Length"
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type(uint8);
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// 2.2.2
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register hciversion ro addr(cap, 0x02) "Host Controller Interface Version Number"
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type(uint16);
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// 2.2.3
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register hcsparams ro addr(cap, 0x04) "Structural parameters" {
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_ 8;
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dpn 4 "Debug port number";
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_ 3;
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p_indicator 1 "Port indicator";
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n_cc 4 "Number of campanion controller";
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n_pcc 4 "Number of ports per companion controller";
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prr 1 "Port routing rules";
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_ 2;
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ppc 1 "Port power control";
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n_ports 4 "Num. physical downstream ports on this controller";
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};
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// 2.2.4
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register hccparams ro addr(cap, 0x08) "Capability parameters" {
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_ 16;
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eecp 8 "EHCI extended capabilities pointer";
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ist 4 "Isochronous scheduling threshold";
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_ 1;
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aspc 1 "Asynchronous sechedule park capability";
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pflf 1 "Programmable frame list flag";
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bit64ac 1 "Extended 64 bit addressing capability";
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};
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// section 2.2.5 Companion port route descriptor
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register hcspportroute ro addr(cap, 0x0C) "Companion port route descr." {
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attr 60 "Port array";
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_ 4;
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};
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/*
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* Section 2.3
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* Host controller operational registers
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*/
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constants itc_val "Interrupt threshold control" {
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itc_val_rsvd = 0x00 "Reserved";
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uframe_1 = 0x01 "1 Micro frame";
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uframes_2 = 0x02 "2 Micro frames";
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uframes_4 = 0x04 "4 Micro frames";
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uframes_8 = 0x08 "8 Micro frames (default, equates to 1 ms)";
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uframes_16 = 0x10 "16 Micro frames (2 ms)";
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uframes_32 = 0x20 "32 Micro frames (4 ms)";
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uframes_64 = 0x40 "64 Micro frames (8 ms)";
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};
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constants frame_val "Frame list size" {
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elem_1024 = 0b00 "1024 Elements (4096 bytes, default)";
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elem_512 = 0b01 "512 Elements (2048 bytes)";
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elem_256 = 0b10 "256 Elements (1024 bytes)";
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frame_rsvd = 0b11 "Reserved";
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};
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// 2.3.1
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register usbcmd rw addr(op, 0x00) "USB command" {
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_ 8 mbz;
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itc 8 type(itc_val) "Interrupt threshold control";
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_ 4 mbz;
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aspme 1 rw "Asynchronous schedule park mode enable";
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_ 1 mbz;
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aspmc 2 rw "Asynchronous schedule park mode count";
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lhcr 1 rw "Light host controller reset";
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iaad 1 rw "Interrupt on async advance doorbell";
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ase 1 rw "Asynchronous schedule enable";
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pse 1 rw "Periodic schedule enable";
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fls 2 type(frame_val) "Frame list size";
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hcr 1 rw "Host controller reset";
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rs 1 rw "Run stop for scheduling";
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};
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// 2.3.2
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register usbsts rw addr(op, 0x04) "USB status" {
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_ 16 mbz;
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ass 1 ro "Asynchronous schedule status";
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pss 1 ro "Periodic schedule status";
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rec 1 ro "Reclamation";
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hch 1 ro "Host controller halted see Run/Stop";
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_ 6 mbz;
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iaa 1 rwc "Interrupt on Async advance";
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hse 1 rwc "Host system error";
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flr 1 rwc "Frame list rollover";
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pcd 1 rwc "Port change detect";
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usbei 1 rwc "USB error interrupt";
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usbi 1 rwc "USB interrupt";
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};
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// 2.3.3
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register usbintr rw addr(op, 0x08) "USB interrupt enable" {
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_ 26 mbz;
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iaae 1 "Interrupt on async advance enable";
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hsee 1 "Host system error enable";
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flre 1 "Frame list rollover enable";
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pcie 1 "Port change interrupt enable";
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usbeie 1 "USB error interrupt enable";
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usbie 1 "USB interrupt enable";
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};
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// 2.3.4
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register frindex rw addr(op, 0x0C) "Frame index" {
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_ 18 mbz;
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fi 14 "Frame index";
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};
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// 2.3.5
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// NOTE: Only enabled if 64 bit address capability is enabled
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register ctrldssegment rw addr(op, 0x10) "Control data structure segment" {
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data 32 rw "MSB [63:32] bits of EHCI data strctures";
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};
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// 2.3.6
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register periodiclistbase rw addr(op, 0x14) "Periodic frame list base addr" {
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addr 20 rw "Base address (must be 4k aligned)";
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_ 12 mbz;
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};
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// 2.3.7
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register asynclistaddr rw addr(op, 0x18) "Current async. list addr." {
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lpl 27 rw "Link pointer low";
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_ 5 mbz;
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};
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// 2.3.8
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register configflag rw addr(op, 0x40) "Configure flag" {
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_ 31 mbz;
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cf 1 rw "Configure flag";
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};
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// 2.3.9
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constants test_mode_val "Test modes" {
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disabled = 0b0000 "Test mode not enabled";
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test_j_st = 0b0001 "Test J_STATE";
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test_k_st = 0b0010 "Test K_STATE";
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se0_nak = 0b0011 "Test SE0_NAK";
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test_pack = 0b0100 "Test packet";
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force_ena = 0b0101 "Force enable";
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};
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constants indi_val "Port indicator values" {
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off = 0b00 "Port indicators are off";
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amber = 0b01 "Amber";
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green = 0b10 "Green";
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indi_val_undef = 0b11 "Undefined";
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};
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constants lstatus_val "USB line status" {
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se0 = 0b00 "Not low speed device, perform EHCI reset";
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j_state = 0b10 "Not low speed device, perform EHCI reset";
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k_state = 0b01 "Low speed device, release ownership of port";
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lstatus_undef = 0b11 "Not low speed device, perform EHCI reset";
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};
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regarray portsc rw addr(op, 0x44)[16] "Port status and control" {
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_ 9 mbz;
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wkoc_e 1 "Wake on over-current enable";
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wkdscnnt_e 1 "Wake on disconnect enable";
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wkcnnt_e 1 "Wake on connect enable";
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ptc 4 type(test_mode_val) "Port test control";
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pic 2 type(indi_val) "Port indicator control";
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po 1 "Port owner";
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pp 1 "Port power";
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ls 2 type(lstatus_val) "Line status value";
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_ 1 mbz;
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pr 1 "Port reset";
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sus 1 "Port suspend";
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fpr 1 "Force port resume";
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occ 1 rwc "Over current change";
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oca 1 ro "Over current active";
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pec 1 rwc "Port enable/disbale change";
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ped 1 "Port enabled/disabled";
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csc 1 rwc "Connect status change";
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ccs 1 ro "Current connect status";
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};
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/*
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//
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// In-memory data structures
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//
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// 3.1
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constants lptype width(2) "Link pointer type" {
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lp_itd = 0b00 "Isochronous transfer descriptor";
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lp_qh = 0b01 "Queue head";
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lp_sitd = 0b10 "Split transaction isochronous trans. desc.";
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lp_fstn = 0b11 "Frame span traversal node";
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};
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datatype lp msbfirst(32) "Link pointer" {
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p 27 "Frame list link pointer";
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_ 2 mbz;
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typ 2 type(lptype) "Pointer type";
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t 1 "Pointer value invalid";
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};
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// 3.3
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datatype itd msbfirst(32) "Isochronous transfer descriptor" {
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next 32 type(lp) "Next descriptor";
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sc0 32 type(itsc) "Transaction 0 Status/control";
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sc1 32 type(itsc) "Transaction 1 Status/control";
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sc2 32 type(itsc) "Transaction 2 Status/control";
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sc3 32 type(itsc) "Transaction 3 Status/control";
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sc4 32 type(itsc) "Transaction 4 Status/control";
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sc5 32 type(itsc) "Transaction 5 Status/control";
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sc6 32 type(itsc) "Transaction 6 Status/control";
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sc7 32 type(itsc) "Transaction 7 Status/control";
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bp0 32 type(itbp0) "Buffer pointer 0";
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bp1 32 type(itbp1) "Buffer pointer 1";
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bp2 32 type(itbp2) "Buffer pointer 2";
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bp3 32 type(itbp3) "Buffer pointer 3";
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bp4 32 type(itbp3) "Buffer pointer 4";
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bp5 32 type(itbp3) "Buffer pointer 5";
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bp6 32 type(itbp3) "Buffer pointer 6";
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};
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// 3.3.2
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datatype itsc msbfirst(32) "Isochronous transaction status/control" {
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// Status
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active 1 "Active";
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dbe 1 "Data buffer error";
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bd 1 "Babble detected";
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xacterr 1 "Transaction error";
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// Control
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length 12 "Transaction length";
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ioc 1 "Interrupt on complete";
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pg 3 "Page select (0-6)";
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offset 12 "Offset from state of buffer";
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};
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// 3.3.3
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datatype itbp0 msbfirst(32) "iTD buffer pointer page 0" {
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p 20 "Buffer pointer (4k aligned)";
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epn 4 "Endpoint number";
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_ 1 mbz;
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da 7 "Device address";
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};
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datatype itdp1 msbfirst(32) "iTD buffer pointer page 1" {
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p 20 "Buffer pointer (4k aligned)";
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dir 1 "In (1) or out (0) PID";
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mps 11 "Maximum packet size";
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};
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datatype itdp2 msbfirst(32) "iTD buffer pointer page 2" {
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p 20 "Buffer pointer (4k aligned)";
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_ 10 mbz;
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multi 2 "Num. transactions/micro-frame + 1 (0=rsvd)";
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};
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datatype itdp3 msbfirst(32) "iTD buffer pointer page 3" {
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p 20 "Buffer pointer (4k aligned)";
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_ 12 mbz;
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};
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// 3.4
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datatype sitd msbfirst(32) "Split isochronous transfer descriptor" {
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next 32 type(lp) "Next descriptor";
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cap 32 type(sitcap) "Endpoint capabilities/characteristics";
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msc 32 type(sitmsc) "Micro-frame schedule control";
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tsc 32 type(sittsc) "Transfer status and control";
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bpl0 32 type(sitbpl0) "Buffer page pointer 0";
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bpl1 32 type(sitbpl1) "Buffer page pointer 1";
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bp 32 type(sitblp) "Back link";
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};
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// 3.4.2
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datatype sitcap msbfirst(32) "siTD endpoint capabilities/characteristics" {
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dir 1 "In (1) or out (0) PID";
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port 7 "Port number";
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_ 1 mbz;
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hub 7 "Hub address";
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_ 4 mbz;
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epn 4 "Endpoint number";
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_ 1 mbz;
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da 7 "Device address";
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};
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datatype sitmsc msbfirst(32) "siTD micro-frame schedule control" {
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_ 16 mbz;
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scm 8 "Split completion mask";
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ssm 8 "Split start mask";
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};
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// 3.4.3
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datatype sittsc msbfirst(32) "siTD transfer status and control" {
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ioc 1 "Interrupt on complete";
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p 1 "Page select";
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_ 4 mbz;
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total 10 "Total bytes to transfer";
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cpm 8 "Microframe complete-split progress mask";
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active 1 "Status active";
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err 1 "ERR response rcvd from transaction translator";
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dbe 1 "Data buffer error";
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babble 1 "Babble detected";
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xacterr 1 "Transaction error";
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mmf 1 "Missed micro-frame";
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sts 1 "Split transaction state";
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_ 1 mbz;
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};
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// 3.4.4
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constants xpos width(2) "Transaction position" {
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tp_all = 0b00 "Entire payload";
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tp_begin = 0b01 "First data payload";
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tp_mid = 0b10 "Middle payload";
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tp_end = 0b11 "Final payload";
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};
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datatype sitbpl0 msbfirst(32) "siTD buffer page pointer list page 0" {
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p 20 "Buffer pointer (4k aligned)";
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offset 12 "Current offset";
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};
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datatype sitbpl1 msbfirst(32) "siTD buffer page pointer list page 1" {
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p 20 "Buffer pointer (4k aligned)";
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_ 7 mbz;
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tp 2 type(xpos) "Transaction position";
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tc 3 "Transaction count";
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};
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// 3.4.5
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datatype sitblp msbfirst(32) "siTD back link pointer" {
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bp 27 "Back pointer";
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_ 4 mbz;
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t 1 "Terminate (0 -> bp is valid)";
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};
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// 3.5
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datatype qtd msbfirst(32) "Queue element transfer descriptor" {
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next 32 type(lp) "Next element";
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altnext 32 type(lp) "Alternate next pointer";
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token 32 type(qttok) "Token";
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bp0 32 type(qtbp0) "Buffer pointer 0";
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bp1 32 type(qtbp1) "Buffer pointer 1";
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bp2 32 type(qtbp1) "Buffer pointer 2";
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bp3 32 type(qtbp1) "Buffer pointer 3";
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bp4 32 type(qtbp1) "Buffer pointer 4";
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};
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// 3.5.3
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constants pid "PID token encoding" {
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pid_out = 0b00 "Generates OUT token (E1H)";
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pid_in = 0b01 "Generates IN token (69H)";
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pid_setup = 0b10 "Generates SETUP token (2DH)";
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pid_rsvd = 0b11 "Reserved";
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};
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datatype qttok msbfirst(32) "qTD Token" {
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toggle 1 "Data toggle";
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tbt 15 "Total bytes to transfer";
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ioc 1 "Interrupt on complete";
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cp 3 "Current page";
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cerr 2 "Error counter";
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pidc 2 type(pid) "PID code token";
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active 1 "Status active";
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halted 1 "Serious error at endpoint";
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dbe 1 "Data buffer error";
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babble 1 "Babble detected";
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xacterr 1 "Transaction error";
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mmf 1 "Missed micro-frame";
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sts 1 "Split transaction state";
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ping 1 "Ping state";
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};
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// 3.5.4
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datatype qtbp0 msbfirst(32) "Queue element buffer pointer page 0" {
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p 20 "Buffer pointer (4k aligned)";
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offset 12 "Current offset";
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};
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datatype qtbp1 msbfirst(32) "Queue element buffer pointer page 1" {
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p 20 "Buffer pointer (4k aligned)";
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_ 12 mbz;
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};
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// 3.6
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datatype qh msbfirst(32) "Queue head" {
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hlp 32 type(lp) "Horizontal link pointer";
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cap1 32 type(qhcap1) "Endpoint capabilities/characteristics 1";
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cap2 32 type(qhcap2) "Endpoint capabilities/characteristics 2";
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current 32 type(lp) "Current element";
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next 32 type(lp) "Next element";
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altnext 32 type(qhlp) "Alternate next pointer";
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token 32 type(qttok) "Token";
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bp0 32 type(qtbp0) "Buffer pointer 0";
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bp1 32 type(qhbp1) "Buffer pointer 1";
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bp2 32 type(qhbp2) "Buffer pointer 2";
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bp3 32 type(qtbp1) "Buffer pointer 3";
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bp4 32 type(qtbp1) "Buffer pointer 4";
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};
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// 3.6.2
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constants speed width(2) "Endpoint speed" {
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fullspeed = 0b00 "Full-speed (12Mbs)";
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lowspeed = 0b01 "Low-speed (1.5Mbs)";
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highspeed = 0b10 "High-speed (480 Mb/s)";
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};
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datatype qhcap1 msbfirst(32) "Endpoint capabilities: queue head word 1"{
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rl 4 "NAK count reload";
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c 1 "Control endpoint flag";
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mpl 11 "Maximum packet length";
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h 1 "Head of reclamation list flag";
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dtc 1 "Data toggle control";
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eps 2 type(speed) "Endpoint speed";
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epn 4 "Endpoint number";
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i 1 "Inactivate on next transaction";
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da 7 "Device address";
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};
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datatype qhcap2 msbfirst(32) "Endpoint capabilities: queue head word 2"{
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mult 2 "High-bandwidth pipe multiplier";
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port 7 "Port number";
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hub 7 "Hub address";
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scm 8 "Split completion mask";
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ism 8 "Interrupt schedule mask";
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};
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// 3.6.3
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datatype qhlpa msbfirst(32) "Alternate queue head link pointer" {
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p 27 "Frame list link pointer";
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nakcnt 4 "NACK counter";
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t 1 "Pointer value invalid";
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};
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datatype qhbp1 msbfirst(32) "Queue head buffer pointer page 1" {
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p 20 "Buffer pointer (4k aligned)";
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_ 4 mbz;
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cpm 8 "Split-transaction complete-split progress";
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};
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datatype qhbp2 msbfirst(32) "Queue head buffer pointer page 2" {
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p 20 "Buffer pointer (4k aligned)";
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sb 7 "S-bytes";
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ft 5 "Split-transaction frame tag";
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};
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// 3.7
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datatype fstm msbfirst(32) "Periodic Frame Span Traversal Node" {
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normal 32 type(lp) "Normal path link pointer";
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back 32 type(lp) "Back path link pointer";
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};*/
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};
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