431 lines
15 KiB
Plaintext
431 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2013, University of Washington. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* e10k_vf.dev
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*
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* DESCRIPTION: Intel 82599 10 GbE Controller Virtual Function
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*
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* Numbers in comments refer to the Intel 82599 10 GbE Controller Datasheet,
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* Revison 2.76, September 2012
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*/
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device e10k_vf lsbfirst ( addr base ) "Intel 82599 10 GbE Controller Virtual Function" {
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/************************************
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* 8.3.5.1 General control registers--VF
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***********************************/
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// 8.3.5.1.1
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register vfctrl wo addr(base, 0x00000) "VF control" {
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_ 26 rsvd;
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rst 1 "Device reset";
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_ 5 rsvd;
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};
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constants lanid "LAN ID" {
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lan_0 = 0b00 "LAN 0";
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lan_1 = 0b01 "LAN 1";
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lan_not_u1 = 0b10 "LAN ID not used";
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lan_not_u2 = 0b11 "LAN ID not used";
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};
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// 8.3.5.1.2
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register vfstatus ro addr(base, 0x00008) "VF status" {
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_ 2;
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lan_id 2 type(lanid) "LAN ID";
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_ 3;
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link_up 1 "Linkup Status Indication";
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_ 2;
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num_vfs 8 "Num VFs";
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iov_active 1 "IOV Active";
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pcie_mes 1 "PCIe Master Enable Status";
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_ 12;
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};
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// 8.3.5.1.3
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constants mac_lnkmode "MAC link mode status" {
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lms_1g = 0b00 "1 GbE";
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lms_10g_par = 0b01 "10 GbE parallel";
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lms_10g_ser = 0b10 "10 GbE serial";
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lms_aneg = 0b11 "auto-negotiation";
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};
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constants link_speed "MAC link speed status" {
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ls_100m = 0b01 "100 Mb/s";
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ls_1g = 0b10 "1 GbE";
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ls_10g = 0b11 "10 GbE";
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};
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register vflinks ro addr(base, 0x00010) "VF Link Status Register" {
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kxsig_det 1 "A signal is present";
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fecsig_det 1 "FEC reports signal detected";
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fecblk_lck 1 "FEC reached block lock";
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krhberr 1 "10GbE serial KR_PCS high error rate";
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krpcsbl 1 "10 GbE serial PCS block lock";
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kxr_annprcv 1 "KX/KX4/KR AN Next Page Received";
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kxr_anprcv 1 "KX/KX4/KR Backplane Auto Negotiation Page Received";
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lnk_stat 1 "Link Up and there was no link down from last time read";
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kx4sig_det 4 "Signal Detect of 10 GbE Parallel (KX4, CX4 or XAUI) (1bit per lane)";
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krsig_det 1 "Signal Detect of 10 GbE serial (KR or SFI)";
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l10g_syncst 4 "10G Parallel lane sync status (1bit per lane)";
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l10g_algst 1 "10 GbE align_status";
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l1g_syncst 1 "1G sync_status";
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kxr_anrxid 1 "KX/KX4/KR Backplane Auto Negotiation Rx Idle";
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l1g_anen 1 "PCS_1 GbE auto-negotiation is enabled";
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l1g_lnken 1 "1 GbE PCS enabled for 1 GbE and SGMII operation";
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l10g_lnken 1 "XGXS Enabled for 10 GbE operation";
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fec_en 1 "Status of forwarderrorcorrection in 10 GbE serial link";
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l10g_seren 1 "Status of 10 GbE serial PCS (KR PCS) for KR or SFI operation";
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sgmii_en 1 "Status of SGMII operation";
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mlink_mode 2 type (mac_lnkmode) "MAC link mode status";
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lnk_speed 2 type (link_speed) "MAC link speed status";
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lnk_up 1 "Link is up";
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kxr_ancomp 1 "KX/KX4/KR backplane auto-negotiation has completed successfully";
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};
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// NYI:
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// 8.3.5.1.4 VF Free Running Timer (VFFRTIMER)
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// 8.3.5.1.5 VF Mailbox (VFMailbox)
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// 8.3.5.1.6 VF Mailbox Memory (VFMBMEM)
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// 8.3.5.1.7
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register vfrxmemwrap ro addr(base, 0x03190) "VF Rx Packet Buffer Flush Detect" {
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tc0_wrap 3 "Packet Buffer 0 Wrap Around Counter";
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tc0_empty 1 "Packet Buffer 0 Empty";
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tc1_wrap 3 "Packet Buffer 1 Wrap Around Counter";
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tc1_empty 1 "Packet Buffer 1 Empty";
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tc2_wrap 3 "Packet Buffer 2 Wrap Around Counter";
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tc2_empty 1 "Packet Buffer 2 Empty";
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tc3_wrap 3 "Packet Buffer 3 Wrap Around Counter";
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tc3_empty 1 "Packet Buffer 3 Empty";
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tc4_wrap 3 "Packet Buffer 4 Wrap Around Counter";
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tc4_empty 1 "Packet Buffer 4 Empty";
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tc5_wrap 3 "Packet Buffer 5 Wrap Around Counter";
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tc5_empty 1 "Packet Buffer 5 Empty";
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tc6_wrap 3 "Packet Buffer 6 Wrap Around Counter";
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tc6_empty 1 "Packet Buffer 6 Empty";
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tc7_wrap 3 "Packet Buffer 7 Wrap Around Counter";
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tc7_empty 1 "Packet Buffer 7 Empty";
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};
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/************************************
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* 8.3.5.2 Interrupt Registers--VF
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***********************************/
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// 8.3.5.2.1
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register vfeicr rw1c addr(base, 0x00100) "VF Extended Interrupt Cause" {
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msix 3 "Indicates an interrupt cause mapped to MSI-X vectors 2:0";
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_ 29 rsvd;
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};
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// 8.3.5.2.2
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register vfeics wo addr(base, 0x00104) "VF Extended Interrupt Cause Set" {
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msix 3 "Sets to corresponding EICR bit of MSI-X vectors 2:0";
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_ 29 rsvd;
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};
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// 8.3.5.2.3
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register vfeims rw addr(base, 0x00108) "VF Extended Interrupt Mask Set/Read" {
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msix 3 "Set mask bit for the corresponding EICR bit of MSI-X vectors 2:0";
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_ 29 rsvd;
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};
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// 8.3.5.2.4
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register vfeimc wo addr(base, 0x0010c) "VF Extended Interrupt Mask Clear" {
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msix 3 "Clear mask bit for the corresponding EICR bit of MSI-X vectors 2:0";
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_ 29 rsvd;
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};
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// 8.3.5.2.5
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register vfeiam rw addr(base, 0x00114) "VF Extended Interrupt Auto Mask Enable" {
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msix 3 "Auto mask bit for the corresponding EICR bit of MSI-X vectors 2:0";
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_ 29 rsvd;
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};
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// 8.3.5.2.6
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/*
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regtype vfeitrn "VF Extended Interrupt Throttle Register Type" {
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_ 3 rsvd;
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itr_int 9 "Minimum inter-interrupt interval";
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_ 3 rsvd;
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lli_mod 1 "LLI Moderation";
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lli_credit 5 "LLI Credit";
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itr_count 7 "ITR Counter";
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_ 3 rsvd;
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cnt_wdis 1 "CNT_WDIS";
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};
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*/
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// XXX: Not sure if this is correct...
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regarray vfeitr rw addr(base, 0x00820) [2]
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"VF Extended Interrupt Mask Set/Read #0-#1"
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type(uint32);
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// 8.3.5.2.7
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regarray vfivar rw addr(base, 0x00120) [4] "VF Interrupt Vector Allocation Registers" {
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i_alloc0 1 "Defines the MSI-X vector (0 or 1) assigned to Rx queue 2*N for IVAR N register (N = 0..3)";
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_ 6 rsvd;
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i_allocval0 1 "Interrupt allocation 0 valid";
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i_alloc1 1 "The interrupt allocation for Tx queue 2n";
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_ 6 rsvd;
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i_allocval1 1 "Interrupt allocation 1 valid";
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i_alloc2 1 "The interrupt allocation for Rx queue 2n+1";
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_ 6 rsvd;
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i_allocval2 1 "Interrupt allocation 2 valid";
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i_alloc3 1 "The interrupt allocation for Tx queue 2n+1";
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_ 6 rsvd;
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i_allocval3 1 "Interrupt allocation 3 valid";
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};
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// 8.3.5.2.8
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register vfivar_misc rw addr(base, 0x00140) "VF Miscellaneous Interrupt Vector Allocation" {
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i_alloc0 2 "MSI-X vector assigned to the mailbox interrupt";
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_ 5 rsvd;
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i_allocval0 1 "Interrupt allocation 0 valid";
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_ 24 rsvd;
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};
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// 8.3.5.2.9
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// XXX: Not sure if this is correct...
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regarray vfrscint rw addr(base, 0x00180) [2] "VF RSC Enable Interrupt" type(uint32);
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// 8.3.5.2.10
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register vfpbacl rw1c addr(base, 0x00148) "VF MSI-X PBA Clear" {
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penbit 3 "MSI-X Pending Bits Clear. Reading returns PBA vector.";
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_ 29 rsvd;
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};
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/************************************
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* 8.3.5.3 Receive DMA Registers -- VF
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***********************************/
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// 8.3.5.3.1
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regarray vfrdbal rw addr(base, 0x01000) [8; 0x40]
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"VF Receive Descriptor Base Address Low (#0-#7)"
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type(uint32);
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// 8.3.5.3.2
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regarray vfrdbah rw addr(base, 0x01004) [8; 0x40]
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"VF Receive Descriptor Base Address High (#0-#7)"
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type(uint32);
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// 8.3.5.3.3
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regarray vfrdlen rw addr(base, 0x01008) [8; 0x40]
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"VF Receive Descriptor Length (#0-#7)"
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type(uint32);
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// 8.3.5.3.4
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regarray vfrdh rw addr(base, 0x01010) [8; 0x40]
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"VF Receive Descriptor Head (#0-#7)"
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type(uint32);
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// 8.3.5.3.5
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regarray vfrdt rw addr(base, 0x01018) [8; 0x40]
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"VF Receive Descriptor Tail (#0-#7)"
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type(uint32);
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// 8.3.5.3.6
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regtype rxdctl "Receive Descriptor Control" {
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_ 25 rsvd;
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enable 1 "Receive Queue Enable";
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_ 4 rsvd;
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vme 1 "VLAN Mode Enable";
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_ 1 rsvd;
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};
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regarray vfrxdctl rw addr(base, 0x01028) [8; 0x40]
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"VF Receive Descriptor Control (#0-#7)"
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type(rxdctl);
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// 8.3.5.3.7
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constants rx_desctype "RX Descriptor Type" {
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legacy = 0b000 "Legacy";
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adv_1buf = 0b001 "Advanced descriptor one buffer";
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adv_hdrsp = 0b010 "Advanced descriptor header splitting";
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adv_usehb = 0b101 "Advanced descriptor header splitting always use header buffer";
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};
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regtype srrctl "Split Receive Control Registers" {
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bsz_pkt 5 "Receive Buffer Size for Packet Buffer";
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_ 3 mbz;
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bsz_hdr 6 "Receive Buffer Size for Header Buffer";
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_ 8 rsvd;
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rdmts 3 "Receive Descriptor Minimum Threshold Size";
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desctype 3 type(rx_desctype) "Define the descriptor type";
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drop_en 1 "Drop Enabled";
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_ 3 rsvd;
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};
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regarray vfsrrctl rw addr(base, 0x01014) [8; 0x40]
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"VF Split Receive Control Registers (#0-#7)"
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type(srrctl);
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// 8.3.5.3.8
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register vfpsrtype rw addr(base, 0x00300) "VF Replication Packet Split Receive Type" {
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_ 1 mbz;
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split_nfs 1 "Split received NFS packets after NFS header";
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_ 2 mbz;
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split_tcp 1 "Split received TCP packets after TCP header";
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split_udp 1 "Split received UDP packets after UDP header";
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_ 2 mbz;
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split_ip4 1 "Split received IPv4 packets after IPv4 header";
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split_ip6 1 "Split received IPv6 packets after IPv6 header";
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_ 2 mbz;
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split_l2 1 "Split received L2 packets after L2 header";
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_ 16 mbz;
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rqpl 3 "Number of bits to use for RSS redirection";
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};
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// 8.3.5.3.9
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constants rsc_maxdesc "Maximum descriptors per Large receive" {
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max_1desc = 0b00 "Maximum of 1 descriptor per large receive";
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max_4desc = 0b01 "Maximum of 4 descriptors per large receive";
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max_8desc = 0b10 "Maximum of 8 descriptors per large receive";
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max_16desc = 0b11 "Maximum of 16 descriptors per large receive";
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};
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regtype rscctl "RSC Control" {
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rsc_en 1 "RSC Enable";
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_ 1 rsvd;
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maxdesc 2 type(rsc_maxdesc) "Maximum descriptors per Large receive";
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_ 28 rsvd;
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};
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regarray vfrscctl rw addr(base, 0x0102c) [8; 0x40]
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"RSC Control (#0-#7)"
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type(rscctl);
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/************************************
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* 8.3.5.4 Transmit Registers -- VF
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***********************************/
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// 8.3.5.4.1
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regarray vftdbal rw addr(base, 0x02000) [4; 0x40]
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"VF Transmit Descriptor Base Address Low"
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type(uint32);
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// 8.3.5.4.2
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regarray vftdbah rw addr(base, 0x02004) [4; 0x40]
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"VF Transmit Descriptor Base Address High"
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type(uint32);
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// 8.3.5.4.3
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regarray vftdlen rw addr(base, 0x02008) [4; 0x40]
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"VF Transmit Descriptor Length"
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type(uint32);
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// 8.3.5.4.4
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// rw is only partially accurate here. This register must only be written
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// directly after reset.
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regarray vftdh rw addr(base, 0x02010) [4; 0x40]
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"VF Transmit Descriptor Head"
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type(uint32);
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// 8.3.5.4.5
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regarray vftdt rw addr(base, 0x02018) [4; 0x40]
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"VF Transmit Descriptor Tail"
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type(uint32);
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// 8.3.5.4.6
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regarray vftxdctl rw addr(base, 0x02028) [4; 0x40] "VF Transmit Descriptor Control" {
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pthresh 7 "Pre-Fetch Threshold";
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_ 1 rsvd;
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hthresh 7 "Host Threshold";
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_ 1 rsvd;
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wthresh 7 "Write-Back Threshold";
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_ 2 rsvd;
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enable 1 "Transmit Queue Enable";
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swflsh 1 "Transmit Software Flush";
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_ 5 rsvd;
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};
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// 8.3.5.4.7
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regarray vftdwbal rw addr(base, 0x02038) [4; 0x40] "VF Tx Descriptor Completion Write Back Address Low" {
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headwb_en 1 "Head Write-Back Enable";
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_ 1 rsvd;
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headwb_low 30 "Lowest 32 bits of the head write-back memory location";
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};
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// 8.3.5.4.8
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regarray vftdwbah rw addr(base, 0x0203c) [4; 0x40] "VF Tx Descriptor Completion Write Back Address High" {
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headwb_high 32 "Highest 32 bits of the head write-back memory location";
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};
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/************************************
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* 8.3.5.5 DCA Registers -- VF
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***********************************/
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// 8.3.5.5.1
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regtype dca_rxctrl "Rx DCA Control Register" {
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_ 5 rsvd;
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rxdca_desc 1 "Descriptor DCA EN";
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rxdca_hdr 1 "Rx Header DCA EN";
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rxdca_payl 1 "Payload DCA EN";
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_ 1 rsvd;
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rxdesc_rdro 1 "Rx Descriptor Read Relax Order Enable";
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_ 1 rsvd;
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rxdesc_wbro 1 mbz "Rx Descriptor Write Back Relax Order Enable";
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_ 1 rsvd;
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rxdata_wrro 1 "Rx data Write Relax Order Enable";
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_ 1 rsvd;
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rxhdr_ro 1 "Rx Split Header Relax Order Enable";
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_ 8 rsvd;
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cpuid 8 "Physical ID";
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};
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regarray vfdca_rxctrl rw addr(base, 0x0100c) [8; 0x40]
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"VF Rx DCA Control Register (#0-#7)"
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type(dca_rxctrl);
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// 8.3.5.5.2
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regarray vfdca_txctrl rw addr(base, 0x0200c) [8; 0x40] "VF Tx DCA Control Registers" {
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_ 5 rsvd;
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txdesc_dca 1 "Descriptor DCA Enable";
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_ 3 rsvd;
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txdesc_rdro 1 "Tx Descriptor Read Relax Order Enable";
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_ 1 rsvd;
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txdesc_wbro 1 "Relax Order Enable of Tx Descriptor well as head pointer write back";
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_ 1 rsvd;
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txdata_rdro 1 "Tx Data Read Relax Order Enable";
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_ 10 rsvd;
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cpuid 8 "Physical ID";
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};
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/************************************
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* 8.3.5.6 Statistics -- VF
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***********************************/
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// 8.3.5.6.1
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register vfgprc ro addr(base, 0x0101c) "VF Good packets received count"
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type(uint32);
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// 8.3.5.6.2
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register vfgptc ro addr(base, 0x0201c) "VF Good packets trasmitted count"
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type(uint32);
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// 8.3.5.6.3
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register vfgorc_lsb ro addr(base, 0x01020) "VF Good Octets Received Count Low"
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type(uint32);
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// 8.3.5.6.4
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register vfgorc_msb ro addr(base, 0x01024) "VF Good Octets Received Count High"
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type(uint32);
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// 8.3.5.6.5
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register vfgotc_lsb ro addr(base, 0x02020) "VF Good Octets Transmitted Count Low"
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type(uint32);
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// 8.3.5.6.6
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register vfgotc_msb ro addr(base, 0x02024) "VF Good Octets Transmitted Count High"
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type(uint32);
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// 8.3.5.6.7
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register vfmprc ro addr(base, 0x01034) "VF Multicast Packets Received Count"
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type(uint32);
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};
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