278 lines
10 KiB
Plaintext
278 lines
10 KiB
Plaintext
/*
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* Copyright (c) 2015, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* cpuid_intel.dev
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*
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* DESCRIPTION: ia32 CPU ID instruction results
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*
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* See:
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* Intel Architecture Manual, Volume 2A, pp. 3-163 - ff., April 2015
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* Table 3-17. Information Returned by CPUID Instruction
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*/
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device cpuid_intel lsbfirst () "ia32 / Intel64 CPUID instruction results" {
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/*
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*============================================================================
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* Basic Information.
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*============================================================================
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*/
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/*
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* CPUID(0, _)
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* ---------------------------------------------------------------------------
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*/
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datatype basic0 lsbfirst (32) "" {
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max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information";
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vendor0 32 rw "Vendor string part 1";
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vendor2 32 rw "Vendor string part 3";
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vendor1 32 rw "Vendor string part 2";
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};
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/*
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* CPUID(1, _)
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* ---------------------------------------------------------------------------
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*/
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constants proc_type width(2) "" {
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original = 0x00 "Original OEM Processor";
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overdrive= 0x01 "Intel OverDrive(r) Processor";
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dual = 0x02 "Dual processor (not applicable to Intel486 processors)";
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reserved = 0x03 "Intel reserved";
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};
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datatype family lsbfirst(32) "" {
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/* Version Information: Type, Family, Model, and Stepping ID (see Figure 3-5) */
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stepping 4 rw "Processor Stepping ID";
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model 4 rw "Processor Model";
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family 4 rw "Processor Family";
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proctype 2 rw "Processor Type";
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_ 2 mbz "Reserved";
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extmodel 4 rw "Extended Model ID";
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extfamily 8 rw "Extended Family ID";
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_ 4 mbz "Reserved";
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};
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/* EAX=1 */
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datatype miscinfo lsbfirst(32) "" {
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brand_idx 8 rw "Brand index";
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cflush_sz 8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)";
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max_log_proc 8 rw "Maximum number of addressable IDs for logical processors";
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/*in this physical package.
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The nearest power-of-2 integer that is not smaller than
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EBX[23:16] is the number of unique initial APIC IDs
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reserved for addressing different logical processors in a
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physical package. */
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init_apicid 8 rw "Initial APIC ID";
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};
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datatype features lsbfirst(32) "" {
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/* Feature Information (see Figure 3-6 and Table 3-19) */
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sse3 1 rw "Streaming SIMD Extensions 3 (SSE3). ";
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pclmulqdq 1 rw "PCLMULQDQ.";
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dtes64 1 rw "64-bit DS Area";
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monitor 1 rw "MONITOR/MWAIT";
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ds_cpl 1 rw "CPL Qualified Debug Store. ";
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vmx 1 rw "Virtual Machine Extensions";
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smx 1 rw "Safer Mode Extensions. ";
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eist 1 rw "Enhanced Intel SpeedStep(r) technology. ";
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tm2 1 rw "Thermal Monitor 2";
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ssse3 1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)";
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cntx_id 1 rw "L1 Context ID. A";
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sdbg 1 rw "IA32_DEBUG_INTERFACE MSR ";
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fma 1 rw "FMA extensions using YMM state.";
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cmpxchg16b 1 rw "CMPXCHG16B Available";
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xtpr 1 rw "xTPR Update Control";
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pdcm 1 rw "Perfmon and Debug Capability";
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_ 1 mbz "";
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pcid 1 rw "Process-context identifiers";
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dca 1 rw "ability to prefetch data from a memory mapped device.";
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sse4_1 1 rw "supports SSE4.1. ";
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sse4_2 1 rw "supports SSE4.2. ";
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x2apic 1 rw "supports x2APIC feature";
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movbe 1 rw "supports MOVBE instruction";
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popcnt 1 rw "supports the POPCNT instruction.";
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tsc_one 1 rw "local APIC timer supports one-shot operation ";
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aesni 1 rw " AESNI instruction extensions";
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xsave 1 rw " XSAVE/XRSTOR processor ";
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osxsave 1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction";
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avx 1 rw "AVX instruction extensions";
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f16c 1 rw "16-bit floating-point conversion instructions.";
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rdrand 1 rw "supports RDRAND instruction.";
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_ 1 mbz "";
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/* Feature Information (see Figure 3-7 and Table 3-20) */
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fpu 1 rw "Floating Point Unit On-Chip";
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vme 1 rw "Virtual 8086 Mode Enhancements";
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de 1 rw "Debugging Extensions. ";
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pse 1 rw "Page Size Extension";
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tsc 1 rw "Time Stamp Counter.";
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msr 1 rw "Model Specific Registers RDMSR and WRMSR Instructions";
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pae 1 rw "Physical Address Extension";
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mce 1 rw "Machine Check Exception. ";
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cx8 1 rw "CMPXCHG8B Instruction.";
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apic 1 rw "APIC On-Chip. ";
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_ 1 mbz "";
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sep 1 rw "SYSENTER and SYSEXIT Instructions.";
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mtrr 1 rw "Memory Type Range Registers";
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pge 1 rw "Page Global Bit";
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mca 1 rw "Machine Check Architecture.";
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cmov 1 rw "Conditional Move Instructions";
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pat 1 rw "Page Attribute Table";
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pse36 1 rw "36-Bit Page Size Extension";
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psn 1 rw "Processor Serial Number. ";
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clfsh 1 rw "CLFLUSH Instruction";
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_ 1 rw "";
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ds 1 rw "Debug Store";
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acpi 1 rw "Thermal Monitor and Software Controlled Clock Facilities";
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mmx 1 rw "Intel MMX Technology";
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fxsr 1 rw "FXSAVE and FXRSTOR Instructions";
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sse 1 rw "SSE1";
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sse2 1 rw "SSE2";
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ss 1 rw "Self Snoop";
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htt 1 rw "Max APIC IDs reserved field is Valid";
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tm 1 rw "Thermal Monitor";
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_ 1 mbz "";
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pbe 1 rw "Pending Break Enable. ";
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};
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/* EAX=2 */
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datatype cache_info lsbfirst (32) "" {
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d0 8 "ignored, always 0x01";
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d1 8 "Descriptor 01";
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d2 8 "Descriptor 02";
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d3 7 "Descriptor 03";
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v0 1 "Contains valid descriptors";
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};
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/* EAX=3 */
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/* not used post P3 */
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/*
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*---------------------------------------------------------------------
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* Deterministic Cache Parameters EAX=4, ECX=idx
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*---------------------------------------------------------------------
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*/
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constants cache_type "Intel Cache Type values" {
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cache_type_null = 0x0 "No more caches";
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cache_type_data = 0x1 "data cache";
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cache_type_instr = 0x2 "Instruction Cache";
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cache_type_unified = 0x3 "Unified Cache";
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};
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/* EAX */
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datatype cache_info_basic lsbfirst (32) "" {
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ctype 5 "Cache Type Field";
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level 3 "Cache Level (starts at 1)";
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selfinit 1 "Self Initializing cache level (does not need SW initialization)";
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fullyassoc 1 "Fully Associative cache";
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_ 4 "Reserved";
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maxlog 12 "Maximum number of addressable IDs for logical processors sharing this cache - 1";
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maxphys 6 "Maximum number of addressable IDs for processor cores in the physical package - 1";
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};
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datatype cache_info_ebx lsbfirst (32) "" {
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coherency 12 "System Coherency Line Size - 1";
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partitions 10 "Physical Line partitions - 1";
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assoc 10 "Ways of associativity - 1";
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};
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datatype cache_info_ecx lsbfirst (32) "" {
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num_sets 32 "The number of Sets - 1";
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};
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datatype cache_info_edx lsbfirst (32) "" {
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wb_inv 1 "Write-Back Invalidate/Invalidate";
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inclusive 1 "Cache Inclusiveness";
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cpx_idx 1 "Complex Cache Indexing";
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_ 29 "";
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};
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/*
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* CPUID(0x16, _) Processor Frequency Information Leaf
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* ---------------------------------------------------------------------------
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*/
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datatype frequency lsbfirst (32) "" {
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mhz 16 "Processor frequency in mhz";
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_ 16 "Reserved";
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};
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/*
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*---------------------------------------------------------------------
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* Extended Information
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*---------------------------------------------------------------------
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*/
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/* extended topology enumaration leaf, eax = 0xb */
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datatype topology_eax lsbfirst (32) "" {
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x2apic_shift 5 "";
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_ 27 "";
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};
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datatype topology_ebx lsbfirst (32) "" {
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logical_proc 16 "";
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_ 16 "";
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};
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datatype topology_ecx lsbfirst (32) "" {
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level_number 8 "";
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level_type 8 "";
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_ 16 "";
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};
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datatype topology_edx lsbfirst (32) "" {
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x2apic 32 "";
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};
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constants topology_level "Intel Cache Type values" {
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topology_level_invalid = 0x0 "Invalid";
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topology_level_smt = 0x1 "SMT";
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topology_level_core = 0x2 "Core";
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topology_level_package = 0x3 "Package";
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};
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/*
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* CPUID(0x80000001, _) Extended Function CPUID Informatio
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* ---------------------------------------------------------------------------
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*/
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datatype features_ext_edx "" {
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_ 11 "";
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syscall 1 "SYSCALL/SYSRET available in 64-bit mode";
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_ 8 "";
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nx 1 "Execute Disable Bit available";
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_ 5 "";
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page1G 1 "1-GByte pages are available if 1";
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rdtscp 1 "RDTSCP and IA32_TSC_AUX are available if 1";
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_ 1 "";
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lm 1 "Intel 64 Architecture available if 1";
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_ 2 "";
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};
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/*
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* CPUID(0x80000008, _)
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* ---------------------------------------------------------------------------
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*/
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datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" {
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physical 8 rw "Maximum physical byte address size in bits";
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linear 8 rw "Maximum linear byte address size in bits. ";
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_ 16 mbz "reserved";
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};
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};
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