326 lines
14 KiB
Plaintext
326 lines
14 KiB
Plaintext
/*
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* Copyright (c) 2015, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* cpuid_amd.dev
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*
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* DESCRIPTION: ia32 CPU ID instruction results
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*
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* See
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* AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008
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*/
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device cpuid_amd lsbfirst () "ia32 / Intel64 CPUID instruction results" {
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/*
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*============================================================================
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* Basic Information.
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*============================================================================
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*/
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/*
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* CPUID(0, _)
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* ---------------------------------------------------------------------------
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*/
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datatype basic lsbfirst (32) "" {
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max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information";
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vendor0 32 rw "Vendor string part 1";
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vendor2 32 rw "Vendor string part 3";
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vendor1 32 rw "Vendor string part 2";
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};
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/*
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* CPUID(1, _)
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* ---------------------------------------------------------------------------
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*/
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datatype family lsbfirst(32) "family information in eax register" {
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stepping 4 rw "Processor Stepping ID";
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model 4 rw "Processor Model";
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family 4 rw "Processor Family";
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_ 4 mbz "Reserved";
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extmodel 4 rw "Extended Model ID";
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extfamily 8 rw "Extended Family ID";
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_ 4 mbz "Reserved";
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};
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datatype miscinfo lsbfirst(32) "info returned in ebx register" {
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brand_idx 8 rw "Brand index";
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cflush_sz 8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)";
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max_log_proc 8 rw "LogicalProcessorCount is the number of cores per processor";
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init_apicid 8 rw "Initial APIC ID";
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};
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datatype features lsbfirst(32) "features returned in {ecx, edx}" {
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/* Feature Information (see Figure 3-6 and Table 3-19) */
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sse3 1 rw "Streaming SIMD Extensions 3 (SSE3). ";
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pclmulqdq 1 rw "PCLMULQDQ.";
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dtes64 1 rw "64-bit DS Area";
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monitor 1 rw "MONITOR/MWAIT";
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ds_cpl 1 rw "CPL Qualified Debug Store. ";
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vmx 1 rw "Virtual Machine Extensions";
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smx 1 rw "Safer Mode Extensions. ";
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eist 1 rw "Enhanced Intel SpeedStep(r) technology. ";
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tm2 1 rw "Thermal Monitor 2";
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ssse3 1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)";
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cntx_id 1 rw "L1 Context ID. A";
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sdbg 1 rw "IA32_DEBUG_INTERFACE MSR ";
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fma 1 rw "FMA extensions using YMM state.";
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cmpxchg16b 1 rw "CMPXCHG16B Available";
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xtpr 1 rw "xTPR Update Control";
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pdcm 1 rw "Perfmon and Debug Capability";
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_ 1 mbz "";
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pcid 1 rw "Process-context identifiers";
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dca 1 rw "ability to prefetch data from a memory mapped device.";
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sse4_1 1 rw "supports SSE4.1. ";
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sse4_2 1 rw "supports SSE4.2. ";
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x2apic 1 rw "supports x2APIC feature";
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movbe 1 rw "supports MOVBE instruction";
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popcnt 1 rw "supports the POPCNT instruction.";
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tsc_one 1 rw "local APIC timer supports one-shot operation ";
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aesni 1 rw " AESNI instruction extensions";
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xsave 1 rw " XSAVE/XRSTOR processor ";
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osxsave 1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction";
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avx 1 rw "AVX instruction extensions";
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f16c 1 rw "16-bit floating-point conversion instructions.";
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rdrand 1 rw "supports RDRAND instruction.";
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_ 1 mbz "";
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/* Feature Information (see Figure 3-7 and Table 3-20) */
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fpu 1 rw "Floating Point Unit On-Chip";
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vme 1 rw "Virtual 8086 Mode Enhancements";
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de 1 rw "Debugging Extensions. ";
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pse 1 rw "Page Size Extension";
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tsc 1 rw "Time Stamp Counter.";
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msr 1 rw "Model Specific Registers RDMSR and WRMSR Instructions";
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pae 1 rw "Physical Address Extension";
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mce 1 rw "Machine Check Exception. ";
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cx8 1 rw "CMPXCHG8B Instruction.";
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apic 1 rw "APIC On-Chip. ";
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_ 1 mbz "";
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sep 1 rw "SYSENTER and SYSEXIT Instructions.";
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mtrr 1 rw "Memory Type Range Registers";
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pge 1 rw "Page Global Bit";
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mca 1 rw "Machine Check Architecture.";
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cmov 1 rw "Conditional Move Instructions";
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pat 1 rw "Page Attribute Table";
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pse36 1 rw "36-Bit Page Size Extension";
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psn 1 rw "Processor Serial Number. ";
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clfsh 1 rw "CLFLUSH Instruction";
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_ 1 rw "";
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ds 1 rw "Debug Store";
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acpi 1 rw "Thermal Monitor and Software Controlled Clock Facilities";
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mmx 1 rw "Intel MMX Technology";
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fxsr 1 rw "FXSAVE and FXRSTOR Instructions";
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sse 1 rw "SSE1";
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sse2 1 rw "SSE2";
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ss 1 rw "Self Snoop";
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htt 1 rw "Max APIC IDs reserved field is Valid";
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tm 1 rw "Thermal Monitor";
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_ 1 mbz "";
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pbe 1 rw "Pending Break Enable. ";
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};
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/*
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* CPUID(0x80000008, _)
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* ---------------------------------------------------------------------------
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*/
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datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" {
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physical 8 rw "Maximum physical byte address size in bits";
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linear 8 rw "Maximum linear byte address size in bits. ";
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guest 8 rw " maximum guest physical byte address size in bits";
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_ 8 mbz "reserved";
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};
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datatype apicid lsbfirst(32) "APIC ID Size and Core Count (ecx)" {
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ncores 8 rw "number of physical cores - 1";
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_ 4 mbz "Reserved";
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apic_sz 4 rw "APIC ID size";
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_ 16 mbz "reserved";
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};
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/*
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* CPUID(0x80000005, _) L1 Cache and TLB Identifiers
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* ---------------------------------------------------------------------------
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*/
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datatype tlb_l1 lsbfirst(32) "" {
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itlb_sz 8 rw "L2 instruction TLB number of entries for 2/4MB pages ";
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itlb_assoc 8 rw "L2 instruction TLB associativity for 2/4MB pages ";
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dtlb_sz 8 rw "L2 data TLB number of entries for 2/4MB pages ";
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dtlb_assoc 8 rw "L2 data TLB associativity for 2/4MB pages";
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};
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datatype l1_2m_tlb lsbfirst(32) "Fn8000_0005_EAX L1 Cache and TLB Identifiers" {
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itlb_sz 8 rw "L2 instruction TLB number of entries for 2/4MB pages ";
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itlb_assoc 8 rw "L2 instruction TLB associativity for 2/4MB pages ";
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dtlb_sz 8 rw "L2 data TLB number of entries for 2/4MB pages ";
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dtlb_assoc 8 rw "L2 data TLB associativity for 2/4MB pages";
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};
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datatype l1_4k_tlb lsbfirst(32) "Fn8000_0005_EBX L1 Cache and TLB Identifiers" {
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itlb_sz 8 rw "L2 instruction TLB number of entries for 4 KB pages. ";
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itlb_assoc 8 rw "L2 instruction TLB associativity for 4 KB pages ";
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dtlb_sz 8 rw "L2 data TLB number of entries for 4 KB pages ";
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dtlb_assoc 8 rw "L2 data TLB associativity for 4 KB pages";
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};
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datatype l1_dcache lsbfirst(32) " Fn8000_0005_ECX L1 Cache and TLB Identifiers" {
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linesize 8 rw "L1 cache line size in bytes. ";
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lines_per_tag 8 rw "L1 cache lines per tag. ";
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assoc 8 rw "L1 cache associativity. See Table 4.";
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size 8 rw "L1 cache size in KB.";
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};
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datatype l1_icache lsbfirst(32) "Fn8000_0005_EDX L1 Cache and TLB Identifiers" {
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linesize 8 rw "L1 cache line size in bytes. ";
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lines_per_tag 8 rw "L1 cache lines per tag. ";
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assoc 8 rw "L1 cache associativity. See Table 4.";
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size 8 rw "L1 cache size in KB.";
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};
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/*
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* CPUID(0x80000006, _) TLB and L2/L3 cache information
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* ---------------------------------------------------------------------------
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*/
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constants cache_assoc "AMD cache associativity values" {
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cache_assoc_disabled = 0x0 "";
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cache_assoc_direct = 0x1 "";
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cache_assoc_2way = 0x2 "";
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cache_assoc_4way = 0x4 "";
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cache_assoc_8way = 0x6 "";
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cache_assoc_16way = 0x8 "";
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cache_assoc_32way = 0xa "";
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cache_assoc_48way = 0xb "";
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cache_assoc_64way = 0xc "";
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cache_assoc_96way = 0xd "";
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cache_assoc_128way = 0xe "";
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cache_assoc_fully = 0xf "";
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};
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datatype tlb_l2 lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" {
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itlb_sz 12 rw "L2 instruction TLB number of entries for 2/4MB pages ";
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itlb_assoc 4 rw "L2 instruction TLB associativity for 2/4MB pages ";
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dtlb_sz 12 rw "L2 data TLB number of entries for 2/4MB pages ";
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dtlb_assoc 4 rw "L2 data TLB associativity for 2/4MB pages";
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};
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datatype l2_2m_tlb lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" {
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itlb_sz 12 rw "L2 instruction TLB number of entries for 2/4MB pages ";
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itlb_assoc 4 rw "L2 instruction TLB associativity for 2/4MB pages ";
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dtlb_sz 12 rw "L2 data TLB number of entries for 2/4MB pages ";
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dtlb_assoc 4 rw "L2 data TLB associativity for 2/4MB pages";
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};
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datatype l2_4k_tlb lsbfirst(32) " Fn8000_0006_EBX L2 TLB Identifiers" {
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itlb_sz 12 rw "L2 instruction TLB number of entries for 4 KB pages. ";
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itlb_assoc 4 rw "L2 instruction TLB associativity for 4 KB pages ";
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dtlb_sz 12 rw "L2 data TLB number of entries for 4 KB pages ";
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dtlb_assoc 4 rw "L2 data TLB associativity for 4 KB pages";
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};
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datatype l2_cache lsbfirst(32) "Fn8000_0006_ECX L2 Cache Identifiers" {
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linesize 8 rw "L2 cache line size in bytes. ";
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lines_per_tag 4 rw "L2 cache lines per tag. ";
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assoc 4 rw "L2 cache associativity. See Table 4.";
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size 16 rw "L2 cache size in KB.";
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};
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datatype l3_cache lsbfirst(32) "Fn8000_0006_EDX L3 Cache Identifiers" {
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linesize 8 rw "L3 cache line size in bytes. ";
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lines_per_tag 4 rw "L3 cache lines per tag. ";
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assoc 4 rw "L3 cache associativity. See Table 4.";
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_ 2 mbz "Reserved";
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size 14 rw "Specifies the L3 cache size in 512kb blocks";
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};
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/*
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* CPUID(0x80000019, _) TLB for 1G Pages
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* ---------------------------------------------------------------------------
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*/
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datatype tlb_1g_l1 lsbfirst(32) "TLB 1GB Page Identifiers eax" {
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itlb_sz 12 "L1 instruction TLB number of entries for 1 GB pages";
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itlb_assoc 4 "L1 instruction TLB associativity for 1 GB pages. See Table 4";
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dtlb_sz 12 "L1 data TLB number of entries for 1 GB pages";
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dtlb_assoc 4 "L1 data TLB associativity for 1 GB pages. See Table 4.";
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};
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datatype tlb_1g_l2 lsbfirst(32) "TLB 1GB Page Identifiers ebx" {
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itlb_sz 12 "L2 instruction TLB number of entries for 1 GB pages";
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itlb_assoc 4 "L2 instruction TLB associativity for 1 GB pages. See Table 4";
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dtlb_sz 12 "L2 data TLB number of entries for 1 GB pages";
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dtlb_assoc 4 "L2 data TLB associativity for 1 GB pages. See Table 4.";
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};
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/*
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* CPUID(0x8000001D, _)
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* ---------------------------------------------------------------------------
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*/
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constants cache_type "AMD Cache Type values" {
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cache_type_null = 0x0 "No more caches";
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cache_type_data = 0x1 "data cache";
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cache_type_instr = 0x2 "Instruction Cache";
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cache_type_unified = 0x3 "Unified Cache";
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};
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/* EAX */
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datatype cache_info_eax lsbfirst (32) "" {
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ctype 5 "Cache Type Field";
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level 3 "Cache Level (starts at 1)";
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selfinit 1 "Self Initializing cache level (does not need SW initialization)";
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fullyassoc 1 "Fully Associative cache";
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_ 4 "Reserved";
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num_sharing 12 "number of cores sharing cache - 1";
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_ 6 "";
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};
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datatype cache_info_ebx lsbfirst (32) "" {
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cachelinesize 12 "cache line size in bytes - 1";
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partitions 10 "cache physical line partitions - 1";
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assoc 10 "cache number of ways - 1";
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};
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datatype cache_info_ecx lsbfirst (32) "" {
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num_sets 32 "The number of Sets - 1";
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};
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datatype cache_info_edx lsbfirst (32) "" {
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wb_inv 1 "Write-Back Invalidate/Invalidate";
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inclusive 1 "Cache Inclusiveness";
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_ 30 "reserved";
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};
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/*
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* CPUID(0x8000001E, _) topology extensions
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* ---------------------------------------------------------------------------
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*/
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datatype ext_apic lsbfirst (32) "register eax" {
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extended_apicid 32 "extended APIC ID";
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};
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datatype cuid lsbfirst (32) "Fn8000_001E_EBX Compute Unit Identifiers" {
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cuid 8 "compute unit id";
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ncores 2 "Number of cores per compute unit - 1";
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_ 22 "Reserved";
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};
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datatype nid lsbfirst (32) "Fn8000_001E_ECX Node Identifiers" {
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nodeid 8 "Specifies the node ID";
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nnodeds 3 "Number of nodes per processor - 1";
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_ 21 "Reserved";
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};
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};
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