527 lines
17 KiB
Plaintext
527 lines
17 KiB
Plaintext
/*
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* Copyright (c) 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* cpuid.dev
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*
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* DESCRIPTION: ia32 CPU ID instruction results
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*
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* See:
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* Intel Architecture Manual, Volume 2A, pp. 3-163 - ff., August 2007
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* AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008
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*/
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device cpuid lsbfirst () "ia32 / Intel64 CPUID instruction results" {
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// We define a different address space for each register
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space eax(i) valuewise "Results in EAX";
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space ebx(i) valuewise "Results in EBX";
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space ecx(i) valuewise "Results in ECX";
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space edx(i) valuewise "Results in EDX";
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//
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// Basic CPUID information
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//
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//
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// EAX=0x00
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//
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register max_biv ro eax(0x00) "Maximum input val for basic CPUID info"
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type(uint32);
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register vendor0 ro ebx(0x00) "Vendor string part 1" type(uint32);
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register vendor1 ro edx(0x00) "Vendor string part 2" type(uint32);
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register vendor2 ro ecx(0x00) "Vendor string part 3" type(uint32);
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//
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// EAX=0x01
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//
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register ver_info ro eax(0x01) "Version information" {
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stepping 4 "Stepping ID";
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model 4 "Model ID";
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family 4 "Family ID";
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proc_type 2 "Processor type (Intel only)";
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_ 2 mbz;
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extmodel 4 "Extended model ID";
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extfamily 8 "Extended family ID";
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_ 4 mbz;
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};
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register brand_ndx ro ebx(0x01) "Brand Index, APIC info" {
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brand 8 "Brand index";
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cflush_sz 8 "CFLUSH line size";
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max_log_proc 8 "Max. # logical processors in this package";
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init_apic_id 8 "Initial local APIC physical ID";
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};
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register feat_info ro edx(0x01) "Feature information" {
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fpu_x87 1 "FPU on chip";
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vme 1 "Virtual-8086 mode enhancement";
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de 1 "Debugging extensions";
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pse 1 "Page size extensions";
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tsc 1 "Time stamp counter";
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msr 1 "RDMSR and WRMSR support";
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pae 1 "Physical address extensions";
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mce 1 "Machine check exception";
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cx8 1 "CMPXCHG8B instruction";
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apic 1 "APIC on chip";
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_ 1;
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sep 1 "SYSENTER and SYSEXIT";
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mtrr 1 "Memory type range registers";
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pge 1 "PTE global bit";
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mca 1 "Machine check architecture";
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cmov 1 "Conditional move/compare instruction";
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pat 1 "Page attribute table";
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pse36 1 "Page size extension";
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psn 1 "Processor serial number";
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clfsh 1 "CFLUSH instruction";
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_ 1;
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ds 1 "Debug store";
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acpi 1 "Thermal monitor and clock control";
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mmx 1 "MMX technology";
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fxsr 1 "FXSAVE / FXRSTOR";
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sse 1 "SSE instructions";
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sse2 1 "SSE2 instructions";
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ss 1 "Self-snoop";
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htt 1 "Multi-threading";
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tm 1 "Thermal monitor";
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_ 1;
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pbe 1 "Pending break enable";
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};
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register ext_feat_info ro ecx(0x01) "Extended feature information" {
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sse3 1 "SSE3 extensions";
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_ 2;
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monitor 1 "MONITOR/MWAIT";
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ds_cpl 1 "CPL qualified debug store";
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vmx 1 "Virtual machine extensions";
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smx 1 "Safer mode extensions";
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est 1 "Enhanced Intel SpeedStep(tm) technology";
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tm2 1 "Thermal monitor 2";
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ssse3 1 "Supplemental SSE3 extensions";
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cnxt_id 1 "L1 context ID";
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_ 2;
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cmpxchg16b 1 "CMPXCHG16B available";
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xtpr_up 1 "xTPR update control";
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pdcm 1 "Perfmon and debug capability";
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_ 3;
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sse4_1 1 "SSE4.1";
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sse4_2 1 "SSE4.2";
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_ 2;
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popcnt 1 "POPCNT instruction";
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_ 8;
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};
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//
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// EAX=0x02 : Cache descriptors (Intel only)
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//
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// Intel, Table 3.17
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constants intel_cache_desc "Intel Cache & TLB descriptors" {
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null_cd = 0x00 "Null descriptor";
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itlb_4k_4w_32 = 0x01 "ITLB, 4k pages, 4-way, 32 entries";
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itlb_4m_4w_2 = 0x02 "ITLB, 4M pages, 4-way, 2 entries";
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dtlb_4k_4w_64 = 0x03 "DTLB, 4k pages, 4-way, 64 entries";
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dtlb_4m_4w_8 = 0x04 "DTLB, 4M pages, 4-way, 8 entries";
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dtlb1_4m_4w_32 = 0x05 "DTLB1, 4M pages, 4-way, 32 entries";
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l1i_8k_4w_32 = 0x06 "L1 Icache, 8k, 4-way, 32b lines";
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l1i_16k_4w_32 = 0x08 "L1 Icache, 16k, 4-way, 32b lines";
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l1d_8k_2w_32 = 0x0a "L1 Dcache, 8k, 2-way, 32b lines";
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itlb_4m_4w_4 = 0x0b "ITLB, 4M pages, 4-way, 4 entries";
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l1d_16k_4w_32 = 0x0c "L1 Dcache, 16k, 4-way, 32b lines";
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l3_512k_4w_64_2 = 0x22 "L3 cache, 512k, 4-way, 64b lines, 2/sector";
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l3_1m_8w_64_2 = 0x23 "L3 cache, 1M, 8-way, 64b lines, 2/sector";
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l3_2m_8w_64_2 = 0x25 "L3 cache, 2M, 8-way, 64b lines, 2/sector";
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l3_4m_8w_64_2 = 0x29 "L3 cache, 4M, 8-way, 64b lines, 2/sector";
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l1d_32k_8w_64 = 0x2c "L1 Dcache, 32k, 8-way, 64b lines";
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l1i_32k_8w_64 = 0x30 "L1 Icache, 32k, 8-way, 64b lines";
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no_l2_l3 = 0x40 "No L2 or L3 cache";
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l2_128k_4w_32 = 0x41 "L2 cache, 128k, 4-way, 32b lines";
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l2_256k_4w_32 = 0x42 "L2 cache, 256k, 4-way, 32b lines";
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l2_512k_4w_32 = 0x43 "L2 cache, 512k, 4-way, 32b lines";
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l2_1m_4w_32 = 0x44 "L2 cache, 1M, 4-way, 32b lines";
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l2_2m_4w_32 = 0x45 "L2 cache, 2M, 4-way, 32b lines";
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l3_4m_4w_64 = 0x46 "L3 cache, 4M, 4-way, 64b lines";
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l3_8m_8w_64 = 0x47 "L3 cache, 8M, 8-way, 64b lines";
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l2_4m_16w_64 = 0x49 "L2 cache, 4M, 16-way, 64b lines";
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itlb_4k2m4n_64 = 0x50 "ITLB, 4k & 2M or 4M pages, 64 entries";
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itlb_4k2m4n_128 = 0x51 "ITLB, 4k & 2M or 4M pages, 128 entries";
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itlb_4k2m4n_256 = 0x52 "ITLB, 4k & 2M or 4M pages, 256 entries";
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dtlb0_4m_4w_16 = 0x56 "DTLB0, 4M pages, 4-way, 16 entries";
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dtlb0_4k_4w_16 = 0x57 "DTLB0, 4k pages, 4-way, 16 entries";
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dtlb_4k4m_64 = 0x5b "DTLB, 4k & 4M pages, 64 entries";
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dtlb_4k4m_128 = 0x5c "DTLB, 4k & 4M pages, 128 entries";
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dtlb_4k4m_256 = 0x5d "DTLB, 4k & 4M pages, 256 entries";
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l1d_16k_8w_64 = 0x60 "L1 Dcache, 16k, 8-way, 64b lines";
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l1d_8k_4w_64 = 0x66 "L1 Dcache, 8k, 4-way, 64b lines";
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l1d_16k_4w_64 = 0x67 "L1 Dcache, 16k, 4-way, 64b lines";
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l1d_32k_4w_64 = 0x68 "L1 Dcache, 32k, 4-way, 64b lines";
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tc_12k_8w = 0x70 "Trace cache, 12k-uop, 8-way";
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tc_16k_8w = 0x71 "Trace cache, 16k-uop, 8-way";
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tc_32k_8w = 0x72 "Trace cache, 32k-uop, 8-way";
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l2_1M_4w_64 = 0x78 "L2 cache, 1M, 4-way, 64b lines";
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l2_128k_8w_64_2 = 0x79 "L2 cache, 128k, 8-way, 64b lines, 2/sector";
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l2_256k_8w_64_2 = 0x7a "L2 cache, 256k, 8-way, 64b lines, 2/sector";
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l2_512k_8w_64_2 = 0x7b "L2 cache, 512k, 8-way, 64b lines, 2/sector";
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l2_1M_8w_64_2 = 0x7c "L2 cache, 1M, 8-way, 64b lines, 2/sector";
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l2_2M_8w_64 = 0x7d "L2 cache, 2M, 8-way, 64b lines";
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l2_512k_2w_64 = 0x7f "L2 cache, 512k, 2-way, 64b lines";
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l2_256k_8w_32 = 0x82 "L2 cache, 256k, 8-way, 32b lines";
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l2_512k_8w_32 = 0x83 "L2 cache, 512k, 8-way, 32b lines";
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l2_1M_8w_32 = 0x84 "L2 cache, 1M, 8-way, 32b lines";
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l2_2M_8w_32 = 0x85 "L2 cache, 2M, 8-way, 32b lines";
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l2_512k_4w_64 = 0x86 "L2 cache, 512k, 4-way, 64b lines";
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l2_1M_8w_64 = 0x87 "L2 cache, 1M, 8-way, 64b lines";
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itlb_4k_4w_128 = 0xb0 "ITLB, 4k pages, 4-way, 128 entries";
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dtlb_4k_4w_128 = 0xb3 "DTLB, 4k pages, 4-way, 128 entries";
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dtlb1_4k_4w_256 = 0xb4 "DTLB1, 4k pages, 4-way, 256 entries";
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pref_64 = 0xf0 "64-byte prefetching";
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pref_128 = 0xf1 "128-byte prefetching";
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};
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/*
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* Exclude this insane mess for now until we really, really need it.
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*
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regtype cache_info "Intel cache/TLB info" {
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d0 8 type(intel_cache_desc) "Descriptor 0";
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d1 8 type(intel_cache_desc) "Descriptor 1";
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d2 8 type(intel_cache_desc) "Descriptor 2";
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d3 7 type(intel_cache_desc) "Descriptor 3";
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valid 1 "Contains valid descriptors";
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};
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register cache_i_a ro eax(0x02) "Intel cache/TLB info eax" type(cache_info);
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register cache_i_b ro ebx(0x02) "Intel cache/TLB info ebx" type(cache_info);
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register cache_i_c ro ecx(0x02) "Intel cache/TLB info ecx" type(cache_info);
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register cache_i_d ro edx(0x02) "Intel cache/TLB info edx" type(cache_info);
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*/
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//
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// EAX=0x03 : Processor serial number (Intel only)
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//
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register pns0 ro ecx(0x03) "Processor serial no. bits 0-31" type(uint32);
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register pns1 ro edx(0x03) "Processor serial no. bits 32-63" type(uint32);
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//
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// EAX=0x04 : Deterministic cache parameters leaf (Intel only)
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//
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constants intel_cachetype "Intel cache type field" {
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ct_null = 0 "Null, no more caches";
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ct_data = 1 "Data cache";
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ct_instruction = 2 "Instruction cache";
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ct_unified = 3 "Unified cache";
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};
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space dcpa(i) valuewise "Deterministic cache parameters leaf A";
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regarray cache_type ro dcpa(0x00)[4] "Cache type information" {
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ctf 5 type(intel_cachetype) "Cache type";
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level 3 "Cache level (starts at 1)";
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self_init 1 "Self initializing";
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fully_assoc 1 "Fully associative";
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wb_inval 1 "Write-back invalidate/invalidate";
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inclusiveness 1 "Cache inclusiveness";
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_ 2;
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max_threads 12 "Max. # threads sharing this cache in package";
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max_procs 6 "Max. # processor cores in this package";
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};
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space dcpb(i) valuewise "Deterministic cache parameters leaf B";
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regarray cache_pars ro dcpb(0x00)[4] "Cache parameters" {
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l 12 "System coherency line size (-1)";
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p 10 "Physical line partitions (-1)";
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w 10 "Ways of associativity (-1)";
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};
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space dcpc(i) valuewise "Deterministic cache parameters leaf C";
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regarray num_sets ro dcpc(0x00)[4] "Number of sets" type(uint32);
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//
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// EAX=0x05 : MONITOR / MWAIT leaf
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//
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register min_monitor ro eax(0x05) "Smallest monitor-line size)" {
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sz 16 "Smallest monitor-line size (bytes)";
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_ 16 mbz;
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};
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register max_monitor ro ebx(0x05) "Largest monitor-line size)" {
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sz 16 "Largest monitor-line size (bytes)";
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_ 16;
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};
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register mwait_feat ro ecx(0x05) "MONITOR/MWAIT features" {
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emx 1 "Supports enum. of Monitor/Mwait extensions";
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ibe 1 "Supports interrupts as break event";
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_ 30;
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};
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register mwait_cstates ro edx(0x05) "sub-C states supported by MWAIT" {
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c0 4 "# C0 sub-C-states supported";
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c1 4 "# C1 sub-C-states supported";
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c2 4 "# C2 sub-C-states supported";
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c3 4 "# C3 sub-C-states supported";
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c4 4 "# C4 sub-C-states supported";
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_ 12 mbz;
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};
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//
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// EAX=0x06 : Thermal and Power Management Leaf (Intel only)
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//
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register tpm_feat ro eax(0x06) "Thermal features" {
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dts 1 "Digital temperature sensor supported";
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ida 1 "Intel dynamic acceleration enabled";
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_ 30 mbz;
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};
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register tpm_thresh ro ebx(0x06) "# interrupt thresholds in sensor" {
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val 4 "# interrupt thresholds in sensor";
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_ 28;
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};
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register tpm_hcfc ro ecx(0x06) "Hardware coordination feedback" {
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en 1 "HCFC present (MCNT/ACNT MSRs)";
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_ 31;
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};
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//
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// EAX=0x0a : Architectural Performance Monitoring Leaf (Intel
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// only)
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register apm_gen ro eax(0x0a) "Gen-purpose perf. counter info" {
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version 8 "Version ID";
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num_counters 8 "# GP perf. counters per logical processor";
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width 8 "Bit width of GP perf. counters";
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vec_length 8 "EBX bit vector length to enumerate events";
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};
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register apm_feat ro ebx(0x0a) "Performance monitoring event availability" {
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cc 1 "Core cycle event";
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ir 1 "Instruction retired";
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rc 1 "Reference cycles";
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llcr 1 "Last-level cache reference";
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llcm 1 "Last-level cache miss";
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bir 1 "Branch instruction retired";
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bmr 1 "Branch mispredict retired";
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_ 25 mbz;
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};
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register apm_fixed ro edx(0x0a) "Fixed-function perf. counter infos" {
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num 5 "# Fixed-function perf. counters";
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width 8 "Width of fixed-function perf. counters";
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_ 19;
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};
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//
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// Extended CPU information
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//
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register ext_biv ro eax(0x80000000) "Max input val for ext. CPUID info"
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type(uint32);
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register evendor0 ro ebx(0x80000000) "Ext. Vendor string pt 1" type(uint32);
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register evendor1 ro edx(0x80000000) "Ext. Vendor string pt 2" type(uint32);
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register evendor2 ro ecx(0x80000000) "Ext. Vendor string pt 3" type(uint32);
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// Mostly AMD only
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register brandid ro ebx(0x80000001) "Brand ID identifier" {
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id 16 "Extended brand ID";
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_ 12;
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pkgtype 4 "Package type";
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};
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register ext_featc ro ecx(0x80000001) "Extend misc. features 1" {
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lahfsahf 1 "LAHF & SAHF support in 64-bit mode";
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cmplegacy 1 "Core multiprocessing legacy mode";
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svm 1 "Secure virtual machine";
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extapicspace 1 "Extended APIC space";
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altmovcr8 1 "LOCK MOV CR0 means MOV CR8";
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abm 1 "Advanced bit manipulation";
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sse4a 1 "EXTRQ/INSERTQ/MOVNTSS/MOVNTSD support";
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misalignsse 1 "Misaligned SSE mode";
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pref3dnow 1 "PREFETCH/PREFETCHW support";
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osvw 1 "OS visible workaround";
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ibs 1 "Instruction-based sampling";
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sse5 1 "SSE 5 instruction support";
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skinit 1 "SKINIT/STGI supported";
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wdt 1 "Watchdog timer support";
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_ 18;
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};
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register ext_featd ro edx(0x80000001) "Extend misc. features 2" {
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_ 11;
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syscallsysret 1 "SYSCALL/SYSRET available in 64-bit mode";
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_ 8;
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nx 1 "No-execute page protection";
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_ 1;
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mmxext 1 "AMD extensions to MMX instructions";
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_ 2;
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ffxsr 1 "FFXSR instruction optimizations";
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page1fb 1 "1-GB large page support";
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rdtscp 1 "RDTSCP instruction";
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_ 1;
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longmode 1 "Long mode / Intel64 available";
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i3dnowext 1 "AMD extensions to 3DNow! instructions";
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i3dnow 1 "3DNow! instructions";
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};
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register brand0 ro eax(0x80000002) "Brand string contd." type(uint32);
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register brand1 ro ebx(0x80000002) "Brand string contd." type(uint32);
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register brand2 ro ecx(0x80000002) "Brand string contd." type(uint32);
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register brand3 ro edx(0x80000002) "Brand string contd." type(uint32);
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register brand4 ro eax(0x80000003) "Brand string contd." type(uint32);
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register brand5 ro ebx(0x80000003) "Brand string contd." type(uint32);
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register brand6 ro ecx(0x80000003) "Brand string contd." type(uint32);
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register brand7 ro edx(0x80000003) "Brand string contd." type(uint32);
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register brand8 ro eax(0x80000004) "Brand string contd." type(uint32);
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register brand9 ro ebx(0x80000004) "Brand string contd." type(uint32);
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register branda ro ecx(0x80000004) "Brand string contd." type(uint32);
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register brandb ro edx(0x80000004) "Brand string contd." type(uint32);
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//
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// EAX=0x80000005 : L1 cache and TLB identifiers (AMD only)
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//
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regtype amd_tlbinfo1 "AMD TLB information" {
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itlb_sz 8 "Number of instruction TLB entries";
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itlb_asc 8 "Instruction TLB associativity";
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dtlb_sz 8 "Number of data DTLB entries";
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dtlb_asc 8 "Data TLB associativity";
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};
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regtype amd_cacheinfo1 "AMD cache information" {
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linesize 8 "line size";
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lpt 8 "lines per tag";
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assoc 8 "associativity";
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size 8 "size in Kb";
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};
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register l1_24m ro eax(0x80000005) "AMD L1 TLB info for 2MB/4MB pages"
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type(amd_tlbinfo1);
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register l1_4k ro ebx(0x80000005) "AMD L1 TLB info for 4k pages"
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type(amd_tlbinfo1);
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register l1_dci ro ecx(0x80000005) "AMD L1 DCache info"
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type(amd_cacheinfo1);
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register l1_ici ro edx(0x80000005) "AMD L1 ICache info"
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type(amd_cacheinfo1);
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//
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// EAX=0x80000006 : L2 cache and TLB identifiers (mostly AMD only)
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//
|
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regtype amd_tlbinfo23 "AMD TLB information" {
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|
itlb_sz 12 "Number of instruction TLB entries";
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|
itlb_asc 4 "Instruction TLB associativity";
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|
dtlb_sz 12 "Number of data DTLB entries";
|
|
dtlb_asc 4 "Data TLB associativity";
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|
};
|
|
regtype amd_cacheinfo23 "AMD cache information" {
|
|
linesize 8 "line size";
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|
lpt 4 "lines per tag";
|
|
assoc 4 "associativity";
|
|
size 16 "size in Kb";
|
|
};
|
|
register l2_24m ro eax(0x80000006) "AMD L2 TLB info for 2MB/4MB pages"
|
|
type(amd_tlbinfo23);
|
|
register l2_4k ro ebx(0x80000006) "AMD L2 TLB info for 4k pages"
|
|
type(amd_tlbinfo23);
|
|
register l2_ci ro ecx(0x80000006) "AMD L2 cache info"
|
|
type(amd_cacheinfo23);
|
|
register l3_ci ro edx(0x80000006) "AMD L3 cache info"
|
|
type(amd_cacheinfo23);
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|
|
|
//
|
|
// EAX=0x80000007 : Advanced Power Management (AMD only)
|
|
//
|
|
|
|
register amd_apm ro edx(0x80000007) "AMD Advanced Power Mgmt" {
|
|
ts 1 "Temperature sensor";
|
|
fid 1 "Frequency ID control";
|
|
vid 1 "Voltage ID control";
|
|
ttp 1 "THERMTRIP";
|
|
tm 1 "Hardware thermal control";
|
|
stc 1 "Software thermal control";
|
|
Mhz100steps 1 "100MHz multiplier control";
|
|
hpwstate 1 "Hardware P-State control";
|
|
tscinvariant 1 "TSC rate invariant";
|
|
_ 23;
|
|
};
|
|
|
|
//
|
|
// EAX=0x80000008 : Address size and physical core count
|
|
//
|
|
|
|
register addr_size ro eax(0x80000008) "Address size" {
|
|
phys 8 "Max physical byte address size in bits";
|
|
linear 8 "Max linear byte address size in bits";
|
|
guest 8 "Max guest physical byte address size in bits";
|
|
_ 8;
|
|
};
|
|
// AMD only
|
|
register core_count ro ecx(0x80000008) "Core count" {
|
|
nc 8 "Number of CPU cores -1 ";
|
|
_ 4;
|
|
apiccoreidsz 4 "APIC core ID size in bits";
|
|
_ 16;
|
|
};
|
|
|
|
//
|
|
// EAX=0x8000000A : SVM revision/feature identification (AMD only)
|
|
//
|
|
|
|
register svmrev ro eax(0x8000000A) "Secure Virtual Machine rev." {
|
|
rev 8 "SVM revision number";
|
|
_ 24;
|
|
};
|
|
register nasid ro ebx(0x8000000A) "# Addr. space identifiers" type(uint32);
|
|
register svmfeat ro edx(0x8000000A) "SVM features" {
|
|
np 1 "Nested paging";
|
|
lbrvirt 1 "LBR virtualization";
|
|
svml 1 "SVM lock";
|
|
nrips 1 "NRIP save";
|
|
_ 5;
|
|
ssse3sse5dis 1 "SSSE3 and SSE5 opcode set disable";
|
|
_ 22;
|
|
};
|
|
|
|
//
|
|
// EAX=0x80000019 : TLB 1GB page identifiers (AMD only)
|
|
//
|
|
|
|
register l1_1G ro eax(0x80000019) "AMD L1 TLB info for 1GB pages"
|
|
type(amd_tlbinfo23);
|
|
register l2_1G ro ebx(0x80000019) "AMD L2 TLB info for 1GB pages"
|
|
type(amd_tlbinfo23);
|
|
|
|
//
|
|
// EAX=0x8000001A : Performance optimization identifiers (AMD only)
|
|
//
|
|
|
|
register opt_id ro eax(0x8000001A) "Perf. optimization identifiers" {
|
|
fp128 1 "128-bit SSE has full-width execution";
|
|
movu 1 "MOVU SSE instructions faster than MOVL";
|
|
_ 30;
|
|
};
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
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|
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