72 lines
1.8 KiB
Plaintext
72 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* arm_icp_pit.dev
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*
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* DESCRIPTION: Timers for for integrator/cp
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*
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* This is derived from:
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*
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* Integrator/CP User Guide
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* (DUI0159B_integratorcp_1_0_ug.pdf)
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*
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*/
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device arm_icp_pit msbfirst ( addr base ) "ARM Integrator timer"
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{
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constants scale "Timer scaling factors" {
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none = 0b00 "none";
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div16 = 0b01 "divide by 16";
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div256 = 0b10 "divide by 256";
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};
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constants mode "Timer Mode" {
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free = 0b0 "Counts once and then wraps to 0xffff";
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reload = 0b1 "Reloads from load register at end of each count";
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};
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register LOAD addr(base, 0x00) "Load value for timer" {
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value 32 rw;
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};
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register CURRENT addr(base, 0x04) "Current value for timer" {
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value 32 ro;
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};
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register CONTROL addr(base, 0x08) "Control register" {
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_ 24;
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enable 1 rw;
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mode 1 rw type(mode);
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int_enable 1 rw;
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_ 1;
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prescale 2 rw type(scale);
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timer32 1 rw "Timer 32-bit (otherwise 16-bit)";
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oneshot 1 rw "Stop rather than wrap.";
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};
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register INTCLR addr(base, 0x0c) "Interrupt clear" {
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value 32 wo;
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};
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register RIS addr(base, 0x10) "Raw interrupt status" {
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_ 31;
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status 1 ro "Raw status";
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};
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register MIS addr(base, 0x14) "Masked interrupt status" {
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_ 31;
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status 1 ro "Masked status";
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};
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register BGLOAD addr(base, 0x18) "Background load value for timer" {
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value 32 rw "Reload value for periodic timer, does not affect CURRENT";
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};
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};
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