76 lines
2.4 KiB
Plaintext
76 lines
2.4 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* arm_icp_pic0.dev
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*
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* DESCRIPTION: Primary interrupt controller for integrator/cp
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*
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* This is derived from:
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*
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* Integrator/CP User Guide
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* (DUI0159B_integratorcp_1_0_ug.pdf)
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*
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*/
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device arm_icp_pic0 msbfirst ( addr base ) "ARM Integrator Primary PIC"
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{
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regtype source "Interrupt controller sources" {
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_ 3;
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TS_PENINT 1 "Touchscreen pen-down event interrupt";
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ETH_INT 1 "Ethernet interface interrupt";
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CPPLDINT 1 "Interrupt from secondary interrupt controller";
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AACIINT 1 "Audio interface interrupt";
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MMCIINT1 1 "MultiMedia card interface 1";
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MMCIINT0 1 "MultiMedia card interface 0";
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CLCDCINT 1 "Display controller interrupt";
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_ 11;
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LM_LLINT1 1 "Logic module low-latency interrupt 1";
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LM_LLINT0 1 "Logic module low-latency interrupt 0";
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RTCINT 1 "Real time clock interrupt";
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TIMERINT2 1 "Counter-timer 2 interrupt";
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TIMERINT1 1 "Counter-timer 1 interrupt";
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TIMERINT0 1 "Counter-timer 0 interrupt";
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MOUSEINT 1 "Mouse interrupt";
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KBDINT 1 "Keyboard interrupt";
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UARTINT1 1 "UART 1 interrupt";
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UARTINT0 1 "UART 0 interrupt";
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SOFTINT 1 "Software interrupt";
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};
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register PIC_IRQ_STATUS ro addr (base, 0x00) "IRQ gated interrupt status"
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type(source);
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register PIC_IRQ_RAWSTAT ro addr (base, 0x04) "IRQ raw interrupt status"
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type(source);
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register PIC_IRQ_ENABLESET rw addr (base, 0x08) "IRQ enable set"
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type(source);
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register PIC_IRQ_ENABLECLR wo addr (base, 0x0c) "IRQ enable clear"
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type(source);
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register PIC_INT_SOFTSET rw addr (base, 0x10) "Software interrupt set"
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type(source);
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register PIC_INT_SOFTCLR wo addr (base, 0x14) "Software interrupt clear"
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type(source);
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register PIC_FIQ_STATUS ro addr (base, 0x20) "FIQ gated interrupt status"
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type(source);
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register PIC_FIQ_RAWSTAT ro addr (base, 0x24) "FIQ raw interrupt status"
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type(source);
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register PIC_FIQ_ENABLESET rw addr (base, 0x28) "FIQ enable set"
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type(source);
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register PIC_FIQ_ENABLECLR wo addr (base, 0x2c) "FIQ enable clear"
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type(source);
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};
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