379 lines
18 KiB
Plaintext
379 lines
18 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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device amd_vmcb lsbfirst ( addr base ) "AMD Virtual Machine Control Block"
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{
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register cr_access addr(base, 0x000) "Intercept reads/writes to CR0-15" {
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rdcr0 1 "Intercept reads of CR0";
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rdcr1 1 "Intercept reads of CR1";
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rdcr2 1 "Intercept reads of CR2";
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rdcr3 1 "Intercept reads of CR3";
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rdcr4 1 "Intercept reads of CR4";
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rdcr5 1 "Intercept reads of CR5";
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rdcr6 1 "Intercept reads of CR6";
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rdcr7 1 "Intercept reads of CR7";
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rdcr8 1 "Intercept reads of CR8";
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rdcr9 1 "Intercept reads of CR9";
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rdcr10 1 "Intercept reads of CR10";
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rdcr11 1 "Intercept reads of CR11";
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rdcr12 1 "Intercept reads of CR12";
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rdcr13 1 "Intercept reads of CR13";
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rdcr14 1 "Intercept reads of CR14";
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rdcr15 1 "Intercept reads of CR15";
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wrcr0 1 "Intercept writes of CR0";
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wrcr1 1 "Intercept writes of CR1";
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wrcr2 1 "Intercept writes of CR2";
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wrcr3 1 "Intercept writes of CR3";
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wrcr4 1 "Intercept writes of CR4";
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wrcr5 1 "Intercept writes of CR5";
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wrcr6 1 "Intercept writes of CR6";
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wrcr7 1 "Intercept writes of CR7";
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wrcr8 1 "Intercept writes of CR8";
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wrcr9 1 "Intercept writes of CR9";
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wrcr10 1 "Intercept writes of CR10";
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wrcr11 1 "Intercept writes of CR11";
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wrcr12 1 "Intercept writes of CR12";
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wrcr13 1 "Intercept writes of CR13";
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wrcr14 1 "Intercept writes of CR14";
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wrcr15 1 "Intercept writes of CR15";
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};
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register dr_access addr(base, 0x004) "Intercept reads/writes to DR0-15" {
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rddr0 1 "Intercept reads of DR0";
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rddr1 1 "Intercept reads of DR1";
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rddr2 1 "Intercept reads of DR2";
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rddr3 1 "Intercept reads of DR3";
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rddr4 1 "Intercept reads of DR4";
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rddr5 1 "Intercept reads of DR5";
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rddr6 1 "Intercept reads of DR6";
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rddr7 1 "Intercept reads of DR7";
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rddr8 1 "Intercept reads of DR8";
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rddr9 1 "Intercept reads of DR9";
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rddr10 1 "Intercept reads of DR10";
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rddr11 1 "Intercept reads of DR11";
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rddr12 1 "Intercept reads of DR12";
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rddr13 1 "Intercept reads of DR13";
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rddr14 1 "Intercept reads of DR14";
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rddr15 1 "Intercept reads of DR15";
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wrdr0 1 "Intercept writes of DR0";
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wrdr1 1 "Intercept writes of DR1";
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wrdr2 1 "Intercept writes of DR2";
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wrdr3 1 "Intercept writes of DR3";
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wrdr4 1 "Intercept writes of DR4";
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wrdr5 1 "Intercept writes of DR5";
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wrdr6 1 "Intercept writes of DR6";
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wrdr7 1 "Intercept writes of DR7";
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wrdr8 1 "Intercept writes of DR8";
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wrdr9 1 "Intercept writes of DR9";
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wrdr10 1 "Intercept writes of DR10";
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wrdr11 1 "Intercept writes of DR11";
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wrdr12 1 "Intercept writes of DR12";
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wrdr13 1 "Intercept writes of DR13";
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wrdr14 1 "Intercept writes of DR14";
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wrdr15 1 "Intercept writes of DR15";
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};
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register exceptions addr(base, 0x008) "Intercept exception vectors 0-31" {
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vector0 1 "Intercept exception vector 0";
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vector1 1 "Intercept exception vector 1";
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vector2 1 "Intercept exception vector 2";
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vector3 1 "Intercept exception vector 3";
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vector4 1 "Intercept exception vector 4";
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vector5 1 "Intercept exception vector 5";
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vector6 1 "Intercept exception vector 6";
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vector7 1 "Intercept exception vector 7";
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vector8 1 "Intercept exception vector 8";
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vector9 1 "Intercept exception vector 9";
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vector10 1 "Intercept exception vector 10";
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vector11 1 "Intercept exception vector 11";
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vector12 1 "Intercept exception vector 12";
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vector13 1 "Intercept exception vector 13";
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vector14 1 "Intercept exception vector 14";
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vector15 1 "Intercept exception vector 15";
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vector16 1 "Intercept exception vector 16";
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vector17 1 "Intercept exception vector 17";
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vector18 1 "Intercept exception vector 18";
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vector19 1 "Intercept exception vector 19";
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vector20 1 "Intercept exception vector 20";
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vector21 1 "Intercept exception vector 21";
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vector22 1 "Intercept exception vector 22";
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vector23 1 "Intercept exception vector 23";
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vector24 1 "Intercept exception vector 24";
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vector25 1 "Intercept exception vector 25";
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vector26 1 "Intercept exception vector 26";
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vector27 1 "Intercept exception vector 27";
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vector28 1 "Intercept exception vector 28";
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vector29 1 "Intercept exception vector 29";
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vector30 1 "Intercept exception vector 30";
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vector31 1 "Intercept exception vector 31";
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};
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register intercepts addr(base, 0x00c) "Various intercepts" {
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intr 1 "Intercept INTR instruction";
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nmi 1 "Intercept NMI instruction";
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smi 1 "Intercept SMI instruction";
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init 1 "Intercept INIT instruction";
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vintr 1 "Intercept VINTR instruction";
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wrcr0 1 "Intercept CR0 writes that change bits other than TS or MP";
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rdidtr 1 "Intercept reads of IDTR";
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rdgdtr 1 "Intercept reads of GDTR";
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rdldtr 1 "Intercept reads of LDTR";
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rdtr 1 "Intercept reads of TR";
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wridtr 1 "Intercept writes of IDRT";
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wrgdtr 1 "Intercept writes of GDTR";
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wrldtr 1 "Intercept writes of LDTR";
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wrtr 1 "Intercept writes of TR";
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rdtsc 1 "Intercept RDTSC instruction";
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rdpmc 1 "Intercept RDPMC instruction";
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pushf 1 "Intercept PUSHF instruction";
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popf 1 "Intercept POPF instruction";
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cpuid 1 "Intercept CPUID instruction";
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rsm 1 "Intercept RSM instruction";
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iret 1 "Intercept IRET instruction";
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intn 1 "Intercept INTn instruction";
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invd 1 "Intercept INVD instruction";
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pause 1 "Intercept PAUSE instruction";
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hlt 1 "Intercept HLT instruction";
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invlpg 1 "Intercept INVLPG instruction";
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invlpga 1 "Intercept INVLPGA instruction";
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ioio_prot 1 "Intercept IN/OUT accesses to selected ports";
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msr_prot 1 "Intercept RDMSR or WRMSR accesses to selected MSRs";
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task_switch 1 "Intercept task switches";
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ferr_freeze 1 "Intercept processor freezing durich legacy FERR handling";
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shutdown 1 "Intercept shutdown events";
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vmrun 1 "Intercept VMRUN instruction";
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vmmcall 1 "Intercept VMMCALL instruction";
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vmload 1 "Intercept VMLOAD instruction";
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vmsave 1 "Intercept VMSAVE instruction";
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stgi 1 "Intercept STGI instruction";
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clgi 1 "Intercept CLGI instruction";
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skinit 1 "Intercept SKINIT instruction";
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rdtscp 1 "Intercept RDTSCP instruction";
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icebp 1 "Intercept ICEBP instruction";
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wbinvd 1 "Intercept WBINVD instruction";
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monitor 1 "Intercept MONITOR instruction";
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mwait0 1 "Intercept MWAIT instruction unconditionally";
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mwait1 1 "Intercept MWAIT instruction if monitor hardware is armed";
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_ 19 rsvd;
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};
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register iopm_base_pa addr(base, 0x040) "Physical base address of IOPM (bits 11:0 are ignored)" type(uint64);
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register msrpm_base_pa addr(base, 0x048) "Physical base address of MSRPM (bits 11:0 are ignored)" type(uint64);
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register tsc_offset addr(base, 0x050) "To be added in RDTSC and RDTSCP" type(uint64);
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register tlb addr(base, 0x058) "Guest TLB settings" {
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guest_asid 32 "Guest ASID";
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control 8 "TLB control values";
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_ 24 rsvd;
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};
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register vintr addr(base, 0x060) "Virtual interrupt settings" {
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vtpr 8 "Virtual TPR for the guest";
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virq 1 "Virtual interrupt pernding";
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_ 7 "Reserved, SBZ";
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vintr_prio 4 "Priority for virtual interrupt";
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v_ign_tpr 1 "Virtual interrupt ignores the virtual TPR";
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_ 3 "Reserved, SBZ";
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vintr_masking 1 "Virtualize masking of INTR interrupt";
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_ 7 "Reserved, SBZ";
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vintr_vector 8 "Vector to use for this interrupt";
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_ 24 rsvd;
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};
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register intr addr(base, 0x068) "Guest interrupt settings" {
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interrupt_shadow 1 "Guest is in an interrupt shadow";
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_ 63 rsvd;
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};
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register exitcode addr(base, 0x070) "Guest EXITCODE" type(uint64);
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register exitinfo1 addr(base, 0x078) "Guest EXITINFO1" type(uint64);
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register exitinfo2 addr(base, 0x080) "Guest EXITINFO2" type(uint64);
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register exitintinfo addr(base, 0x088) "Guest EXITINTINFO" type(uint64);
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register np addr(base, 0x090) "Nested paging settings" {
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enable 1 "Enable nested paging";
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_ 63 rsvd;
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};
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register eventinj addr(base, 0x0a8) "Event injection" type(uint64);
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register ncr3 addr(base, 0x0b0) "Nested page table CR3 to use for nested paging" type(uint64);
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register lbr addr(base, 0x0b8) "Guest LBR settings" {
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lbr_virtualization_enable 1 "Enable LBR virtualization";
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_ 63 rsvd;
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};
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/* Guest State */
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regtype seg_attrib "Segment attributes" {
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segtype 4 "Segment type";
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s 1 "Segment descriptor type";
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dpl 2 "Descriptor privilege level";
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p 1 "Segment present";
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avl 1 "Available for use by system software";
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l 1 "64-bit code segment";
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db 1 "Default operation size (0: 16-bit, 1: 32-bit segment)";
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g 1 "Granularity";
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_ 4 rsvd;
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};
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register es_selector addr(base, 0x400) "Guest ES selector" type(uint16);
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register es_attrib addr(base, 0x402) "Guest ES attrib" type(seg_attrib);
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register es_limit addr(base, 0x404) "Guest ES limit" type(uint32);
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register es_base addr(base, 0x408) "Guest ES base" type(uint64);
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register cs_selector addr(base, 0x410) "Guest CS selector" type(uint16);
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register cs_attrib addr(base, 0x412) "Guest CS attrib" type(seg_attrib);
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register cs_limit addr(base, 0x414) "Guest CS limit" type(uint32);
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register cs_base addr(base, 0x418) "Guest CS base" type(uint64);
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register ss_selector addr(base, 0x420) "Guest SS selector" type(uint16);
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register ss_attrib addr(base, 0x422) "Guest SS attrib" type(seg_attrib);
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register ss_limit addr(base, 0x424) "Guest SS limit" type(uint32);
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register ss_base addr(base, 0x428) "Guest SS base" type(uint64);
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register ds_selector addr(base, 0x430) "Guest DS selector" type(uint16);
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register ds_attrib addr(base, 0x432) "Guest DS attrib" type(seg_attrib);
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register ds_limit addr(base, 0x434) "Guest DS limit" type(uint32);
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register ds_base addr(base, 0x438) "Guest DS base" type(uint64);
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register fs_selector addr(base, 0x440) "Guest FS selector" type(uint16);
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register fs_attrib addr(base, 0x442) "Guest FS attrib" type(seg_attrib);
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register fs_limit addr(base, 0x444) "Guest FS limit" type(uint32);
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register fs_base addr(base, 0x448) "Guest FS base" type(uint64);
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register gs_selector addr(base, 0x450) "Guest GS selector" type(uint16);
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register gs_attrib addr(base, 0x452) "Guest GS attrib" type(seg_attrib);
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register gs_limit addr(base, 0x454) "Guest GS limit" type(uint32);
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register gs_base addr(base, 0x458) "Guest GS base" type(uint64);
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register gdtr_selector addr(base, 0x460) "Guest GTDR selector" type(uint16);
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register gdtr_attrib addr(base, 0x462) "Guest GTDR attrib" type(seg_attrib);
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register gdtr_limit addr(base, 0x464) "Guest GTDR limit" type(uint32);
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register gdtr_base addr(base, 0x468) "Guest GTDR base" type(uint64);
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register ldtr_selector addr(base, 0x470) "Guest LTDR selector" type(uint16);
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register ldtr_attrib addr(base, 0x472) "Guest LTDR attrib" type(seg_attrib);
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register ldtr_limit addr(base, 0x474) "Guest LTDR limit" type(uint32);
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register ldtr_base addr(base, 0x478) "Guest LTDR base" type(uint64);
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register idtr_selector addr(base, 0x480) "Guest ITDR selector" type(uint16);
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register idtr_attrib addr(base, 0x482) "Guest ITDR attrib" type(seg_attrib);
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register idtr_limit addr(base, 0x484) "Guest ITDR limit" type(uint32);
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register idtr_base addr(base, 0x488) "Guest ITDR base" type(uint64);
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register tr_selector addr(base, 0x490) "Guest TR selector" type(uint16);
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register tr_attrib addr(base, 0x492) "Guest TR attrib" type(seg_attrib);
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register tr_limit addr(base, 0x494) "Guest TR limit" type(uint32);
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register tr_base addr(base, 0x498) "Guest TR base" type(uint64);
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register cpl addr(base, 0x4cb) "Guest current protection level" type(uint8);
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register efer addr(base, 0x4d0) "Guest EFER" {
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sce 1 "System Call Extensions";
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_ 7 mbz;
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lme 1 "Long Mode Enable";
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_ 1 mbz;
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lma 1 "Long Mode Active";
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nxe 1 "No-Execute Enable";
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svme 1 "Secure Virtual Machine Enable";
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_ 1 mbz;
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ffxsr 1 "Fast FXSAVE/FXRSTOR";
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_ 49 mbz;
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};
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register cr4 addr(base, 0x548) "Guest CR4" {
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vme 1 "Virtual-8086 Mode Extensions";
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pvi 1 "Protected-Mode Virtual Interrupts";
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tsd 1 "Time Stamp Disable";
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de 1 "Debugging Extensions";
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pse 1 "Page Size Extensions";
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pae 1 "Physical-Address Extension";
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mce 1 "Machine Check Enable";
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pge 1 "Page-Global Enable";
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pce 1 "Performance-Monitoring Counter Enable";
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osfxsr 1 "Operating System FXSAVE/FXRSTOR Support";
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osxmmecept 1 "Operating System Unmasked Exception Support";
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_ 53 mbz;
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};
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register cr3 addr(base, 0x550) "Guest CR3" type(uint64);
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register cr0 addr(base, 0x558) "Guest CR0" {
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pe 1 "Protection Enabled";
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mp 1 "Monitor Coprocessor";
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em 1 "Emulation";
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ts 1 "Task Switched";
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et 1 ro "Extension Type";
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ne 1 "Numeric Error";
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_ 10 rsvd;
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wp 1 "Write Protect";
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_ 1 rsvd;
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am 1 "Alignment Mask";
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_ 10 rsvd;
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nw 1 "Not Writethrough";
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cd 1 "Cache Disable";
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pg 1 "Paging";
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_ 32 mbz;
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};
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register dr7 addr(base, 0x560) "Guest DR7" type(uint64);
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register dr6 addr(base, 0x568) "Guest DR6" type(uint64);
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register rflags addr(base, 0x570) "Guest RFLAGS" {
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cf 1 "Carry Flag";
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_ 1 rsvd;
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pf 1 "Parity Flag";
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_ 1 rsvd;
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af 1 "Auxiliary Flag";
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_ 1 rsvd;
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zf 1 "Zero Flag";
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sf 1 "Sign Flag";
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tf 1 "Trap Flag";
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intrf 1 "Interrupt Flag";
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df 1 "Direction Flag";
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of 1 "Overflow Flag";
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iopl 2 "I/O Privilege Level";
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nt 1 "Nested Task";
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_ 1 rsvd;
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rf 1 "Resume Flag";
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vm 1 "Virtual-8086 Mode";
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ac 1 "Alignment Check";
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vif 1 "Virtual Interrupt Flag";
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vip 1 "Virtual Interrupt Pending";
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id 1 "ID Flag";
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_ 42 rsvd;
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};
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register rip addr(base, 0x578) "Guest RIP" type(uint64);
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register rsp addr(base, 0x5d8) "Guest RSP" type(uint64);
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register rax addr(base, 0x5F8) "Guest RAX" type(uint64);
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register star addr(base, 0x600) "Guest STAR" type(uint64);
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register lstar addr(base, 0x608) "Guest LSTAR" type(uint64);
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register cstar addr(base, 0x610) "Guest CSTAR" type(uint64);
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register sfmask addr(base, 0x618) "Guest SFMASK" type(uint64);
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register kernel_gs_base addr(base, 0x620) "Guest KernelGsBase" type(uint64);
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register sysenter_cs addr(base, 0x628) "Guest SYSENTER_CS" type(uint64);
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register sysenter_esp addr(base, 0x630) "Guest SYSENTER_ESP" type(uint64);
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register sysenter_eip addr(base, 0x638) "Guest SYSENTER_EIP" type(uint64);
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register cr2 addr(base, 0x640) "Guest CR2" type(uint64);
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register gpat addr(base, 0x668) "Guest PAT" type(uint64);
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register dbgctl addr(base, 0x670) "Guest DBGCTL MSR" type(uint64);
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register br_from addr(base, 0x678) "Guest LastBranchFromIP MSR" type(uint64);
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register br_to addr(base, 0x680) "Guest LastBranchToIP MSR" type(uint64);
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register lastexcpfrom addr(base, 0x688) "Guest LastExceptionFromIP MSR" type(uint64);
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register lastexcpto addr(base, 0x690) "Guest LastExceptionToIP MSR" type(uint64);
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};
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