137 lines
3.6 KiB
Plaintext
137 lines
3.6 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* ahci_hba.dev
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*
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* DESCRIPTION: AHCI (SATA) Host bus adaptor, generic registers (ports
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* have their own devive definition.
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*
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* Section numbers refer to the Serial ATA Advanced Host Controller
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* Interface (AHCI) specification 1.3, June 2008
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*/
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device ahci_hba msbfirst (addr b) "AHCI generic" {
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// 3.1.1
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constants speed "Interface speed" {
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gen1 = 0b0001 "Gen 1 (1.5 Gbps)";
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gen2 = 0b0010 "Gen 2 (3 Gbps)";
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gen3 = 0b0011 "Gen 3 (6 Gbps)";
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};
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register cap ro addr(b,0x00) "HBA capabilities" {
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s64a 1 "Supports 64-bit addressing";
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sncq 1 "Supports native command queueing";
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ssntf 1 "Supports SNotification register";
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smps 1 "Supports mechanical presence switch";
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sss 1 "Supports staggered spin-up";
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salp 1 "Supports aggressive link power management";
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sal 1 "Supports activity LED";
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sclo 1 "Supports command list override";
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iss 4 type(speed) "Interface speed support";
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_ 1 rsvd;
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sam 1 "Supports AHCI mode only";
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spm 1 "Supports port multiplier";
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fbss 1 "FIS-based switching supported";
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pmd 1 "PIO multiple DRQ block";
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ssc 1 "Slumber state capable";
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psc 1 "Partial state capable";
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ncs 5 "Number of command slots";
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cccs 1 "Command completion coalescing supported";
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ems 1 "Enclosure management supported";
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sxs 1 "Supports external SATA";
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np 5 "Number of ports";
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};
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// 3.1.2
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register ghc rw addr(b,0x04) "Global HBA control" {
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ae 1 rw "AHCI enable";
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_ 28 rsvd;
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mrsm 1 ro "MSI revert to single message";
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ie 1 rw "Interrupt enable";
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hr 1 rw "HBA reset";
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};
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// 3.1.3
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register is rwc addr(b,0x08) "Interrupt status" type(uint32);
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// 3.1.4
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register pi ro addr(b,0x0c) "Ports implemented" type(uint32);
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// 3.1.5
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register vs ro addr(b,0x10) "AHCI version" {
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major 16 "Major version";
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minor 16 "Minor version";
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};
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// 3.1.6
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register ccc_ctl rw addr(b,0x14) "Command completion coalescing control" {
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tv 16 "Timeout value";
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cc 8 "Command completions";
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intr 5 ro "Interrupt";
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_ 2 rsvd;
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en 1 "Enable";
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};
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// 3.1.7
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register ccc_ports rw addr(b,0x18) "Command completions coalescing ports"
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type(uint32);
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// 3.1.8
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register em_loc ro addr(b,0x1c) "Enclosure management location" {
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ofst 16 "Offset";
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sz 16 "Bufer size";
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};
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// 3.1.9
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register em_ctl addr(b,0x20) "Enclosure management control" {
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_ 4 rsvd;
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pm 1 ro "Port multiplier support";
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alhd 1 ro "Activity LED hardware driven";
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xmt 1 ro "Transmit only";
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smb 1 ro "Single message buffer";
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_ 4 rsvd;
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sgpio 1 ro "SGPIO enclosure management messages";
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ses2 1 ro "SES-2 enclosure management messages";
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safte 1 ro "SAF-TE enclosure management messages";
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led 1 ro "LED message types";
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_ 6 rsvd;
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rst 1 rw "Reset";
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tm 1 rw "Transmit message";
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_ 7 rsvd;
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mr 1 rw1c "Message received";
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};
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// 3.1.10
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register cap2 ro addr(b,0x24) "HBA capabilities extended" {
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_ 29 rsvd;
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apst 1 "Automatic partial to slumber transitions";
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nvmp 1 "NVMHCI present";
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boh 1 "BIOS/OS handoff";
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};
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// 3.1.11
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register bohc addr(b,0x28) "BIOS/OS handoff control and status" {
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_ 27 rsvd;
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bb 1 rw "BIOS busy";
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ooc 1 rw1c "OS ownership change";
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sooe 1 rw "SMI on OS ownership change enable";
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oos 1 rw "OS owned semaphore";
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bos 1 rw "BIOS owned semaphore";
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};
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};
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