/*
 * Copyright (c) 2014 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
 */

/*
 * xeon_phi_smpt.dev
 *
 * description: register definitions for the Xeon Phi system memory page tables
 */

device xeon_phi_smpt lsbfirst ( addr base ) "Intel Xeon Phi System Memory Page Tables" {

    /*
     * Protection Level: Ring 0
     * Visibility: Host / Coprocessor
     * Reset Dmain: CSR_RESET, HOT_RESET
     * Register Access: TRM
     * Number: 32
     */
    regarray entry rw addr(base, 3100) [32] "System Memory Page Table Entry" { 
        value 32 "Value";
    };


};