/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_cam_prm.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_cam_prm msbfirst ( addr base ) "" {
    

    constants cam_mem_onstate_status width(2) "" {
        CAM_MEM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON.";
    };

    constants lowpowerstatechange_status width(1) "" {
        LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change.";
        LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON.";
    };

    constants powerstate_status width(2) "" {
        POWERSTATE_0 = 0 "OFF state";
        POWERSTATE_1_r = 1 "Reserved";
        POWERSTATE_2 = 2 "INACTIVE state";
        POWERSTATE_3 = 3 "ON State";
    };
    
    register pm_cam_pwrstctrl addr(base, 0x0) "This register controls the CAM power state to reach upon a domain sleep transition" {
        _ 14 mbz;
        cam_mem_onstate 2 ro type(cam_mem_onstate_status) "CAM_MEM memory state when domain is ON.";
        _ 11 mbz;
        lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain.";
        _ 2 mbz;
        powerstate 2 rw type(powerstate_status) "Power state control";
    };

    constants lastpowerstateentered_status width(2) "" {
        LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE";
        LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE";
        LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION";
        LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF";
    };

    constants intransition_status width(1) "" {
        INTRANSITION_1_r = 1 "Power domain transition is in progress.";
        INTRANSITION_0_r = 0 "No on-going transition on power domain";
    };

    constants cam_mem_statest_status width(2) "" {
        CAM_MEM_STATEST_3_r = 3 "Memory is ON";
        CAM_MEM_STATEST_2_r = 2 "Reserved";
        CAM_MEM_STATEST_1_r = 1 "Reserved";
        CAM_MEM_STATEST_0_r = 0 "Memory is OFF";
    };

    constants logicstatest_status width(1) "" {
        LOGICSTATEST_1_r = 1 "Logic in domain is ON";
        LOGICSTATEST_0_r = 0 "Logic in domain is OFF";
    };

    constants powerstatest_status width(2) "" {
        POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE";
        POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE";
        POWERSTATEST_1_r = 1 "Power domain is in RETENTION";
        POWERSTATEST_0_r = 0 "Power domain is OFF";
    };
    
    register pm_cam_pwrstst addr(base, 0x4) "This register provides a status on the current CAM power domain state. [warm reset insensitive]" {
        _ 6 mbz;
        lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only.";
        _ 3 mbz;
        intransition 1 ro type(intransition_status) "Domain transition status";
        _ 14 mbz;
        cam_mem_statest 2 ro type(cam_mem_statest_status) "CAM_MEM memory state status";
        _ 1 mbz;
        logicstatest 1 ro type(logicstatest_status) "Logic state status";
        powerstatest 2 ro type(powerstatest_status) "Current power state status";
    };

    constants lostmem_cam_mem_status width(1) "" {
        LOSTMEM_CAM_MEM_0 = 0 "Context has been maintained";
        LOSTMEM_CAM_MEM_1 = 1 "Context has been lost";
    };
    
    register rm_cam_iss_context addr(base, 0x24) "This register contains dedicated ISS context statuses. [warm reset insensitive]" {
        _ 23 mbz;
        lostmem_cam_mem 1 rw1c type(lostmem_cam_mem_status) "Specify if memory-based context in CAM_MEM memory bank has been lost due to a previous power transition or other reset source.";
        _ 7 mbz;
        lostcontext_dff 1 rw1c type(lostmem_cam_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)";
    };
    
    register rm_cam_fdif_context addr(base, 0x2C) "This register contains dedicated FDIF context statuses. [warm reset insensitive]" {
        _ 23 mbz;
        lostmem_cam_mem 1 rw1c type(lostmem_cam_mem_status) "Specify if memory-based context in CAM_MEM memory bank has been lost due to a previous power transition or other reset source.";
        _ 7 mbz;
        lostcontext_dff 1 rw1c type(lostmem_cam_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)";
    };
};