/* * Copyright (c) 2013 ETH Zurich. All rights reserved. * * This file is distributed under the terms in the attached LICENSE file. * If you do not find this file, copies can be found by writing to: * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, * Attn: Systems Group. */ /* * omap44xx_dss_prm.dev * * DESCRIPTION: * * NOTE: This file has been automatically generated based on the * XML files extracted from the TI RDT v1.0.0.4p Tool. * Download from here: http://www.ti.com/product/omap4460 * This means that the file might not be optimal in terms of naming * conventions for constants and registers (duplicated * namespaces in register and device name etc.). * Also, because of the underlying structure from the original XML * it's possible that some constants appear multiple times (if they * have slightly different descriptions for example). * * You want to clean that up before using the files for the first time! */ device omap44xx_dss_prm msbfirst ( addr base ) "" { constants dss_mem_onstate_status width(2) "" { DSS_MEM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; }; constants dss_mem_retstate_status width(1) "" { DSS_MEM_RETSTATE_0_r = 0 "Memory bank is off when the domain is in the RETENTION state."; }; constants lowpowerstatechange_status width(1) "" { LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change."; LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON."; }; constants powerstate_status width(2) "" { POWERSTATE_0 = 0 "OFF state"; POWERSTATE_1 = 1 "RETENTION state"; POWERSTATE_2 = 2 "INACTIVE state"; POWERSTATE_3 = 3 "ON State"; }; register pm_dss_pwrstctrl addr(base, 0x0) "This register controls the DSS power state to reach upon a domain sleep transition" { _ 14 mbz; dss_mem_onstate 2 ro type(dss_mem_onstate_status) "DSS_MEM state when domain is ON."; _ 7 mbz; dss_mem_retstate 1 ro type(dss_mem_retstate_status) "DSS_MEM state when domain is RETENTION."; _ 3 mbz; lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."; _ 1 mbz; logicretstate 1 ro type(dss_mem_retstate_status) "Logic state when power domain is RETENTION"; powerstate 2 rw type(powerstate_status) "Power state control"; }; constants lastpowerstateentered_status width(2) "" { LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously OFF"; LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously in RETENTION"; LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously ON-INACTIVE"; LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously ON-ACTIVE"; }; constants intransition_status width(1) "" { INTRANSITION_0_r = 0 "No ongoing transition on power domain"; INTRANSITION_1_r = 1 "Power domain transition is in progress."; }; constants dss_mem_statest_status width(2) "" { DSS_MEM_STATEST_0_r = 0 "Memory is OFF"; DSS_MEM_STATEST_1_r = 1 "Reserved"; DSS_MEM_STATEST_2_r = 2 "Reserved"; DSS_MEM_STATEST_3_r = 3 "Memory is ON"; }; constants logicstatest_status width(1) "" { LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; LOGICSTATEST_1_r = 1 "Logic in domain is ON"; }; constants powerstatest_status width(2) "" { POWERSTATEST_0_r = 0 "Power domain is OFF"; POWERSTATEST_1_r = 1 "Power domain is in RETENTION"; POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE"; POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; }; register pm_dss_pwrstst addr(base, 0x4) "This register provides a status on the current DSS power domain state. [warm reset insensitive]" { _ 6 mbz; lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."; _ 3 mbz; intransition 1 ro type(intransition_status) "Domain transition status"; _ 14 mbz; dss_mem_statest 2 ro type(dss_mem_statest_status) "DSS_MEM state status"; _ 1 mbz; logicstatest 1 ro type(logicstatest_status) "Logic state status"; powerstatest 2 ro type(powerstatest_status) "Current power state status"; }; constants wkupdep_hdmidma_sdma_status width(1) "" { WKUPDEP_HDMIDMA_SDMA_1_r = 1 "Dependency is enabled"; }; constants wkupdep_hdmiirq_dsp_status width(1) "" { WKUPDEP_HDMIIRQ_DSP_0 = 0 "Dependency is disabled"; WKUPDEP_HDMIIRQ_DSP_1 = 1 "Dependency is enabled"; }; register pm_dss_dss_wkdep addr(base, 0x20) "This register controls wakeup dependency based on DSS service requests." { _ 12 mbz; wkupdep_hdmidma_sdma 1 ro type(wkupdep_hdmidma_sdma_status) "Wakeup dependency from HDMI module (SWakeup_HDMI_dma signal) towards SDMA + L3_2 domains"; _ 4 mbz; wkupdep_hdmiirq_dsp 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from HDMI module (softwareakeup_HDMI_irq signal) towards DSP + L3_1 + L3_2 domains"; wkupdep_hdmiirq_mpu_m3 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from HDMI module (softwareakeup_HDMI_irq signal) towards MPU_A3 + L3_2 domains"; wkupdep_hdmiirq_mpu 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from HDMI module (softwareakeup_HDMI_irq signal) towards MPU + L3_1 + L3_2 domains"; wkupdep_dsi2_sdma 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards SDMA + L3_2 domains"; wkupdep_dsi2_dsp 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards DSP + L3_1 + L3_2 domains"; wkupdep_dsi2_mpu_m3 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards MPU_A3 + L3_2 domains"; wkupdep_dsi2_mpu 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards MPU + L3_1 + L3_2 domains"; wkupdep_dsi1_sdma 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards SDMA + L3_2 domains"; wkupdep_dsi1_dsp 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards DSP + L3_1 + L3_2 domains"; wkupdep_dsi1_mpu_m3 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards MPU_A3 + L3_2 domains"; wkupdep_dsi1_mpu 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards MPU + L3_1 + L3_2 domains"; wkupdep_dispc_sdma 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards SDMA + L3_2 domains"; wkupdep_dispc_dsp 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards DSP + L3_1 + L3_2 domains"; wkupdep_dispc_mpu_m3 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards MPU_A3 + L3_2 domains"; wkupdep_dispc_mpu 1 rw type(wkupdep_hdmiirq_dsp_status) "Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards MPU + L3_1 + L3_2 domains"; }; constants lostmem_dss_mem_status width(1) "" { LOSTMEM_DSS_MEM_0 = 0 "Context has been maintained"; LOSTMEM_DSS_MEM_1 = 1 "Context has been lost"; }; register rm_dss_dss_context addr(base, 0x24) "This register contains dedicated DSS context statuses. [warm reset insensitive]" { _ 23 mbz; lostmem_dss_mem 1 rw1c type(lostmem_dss_mem_status) "Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source."; _ 6 mbz; lostcontext_rff 1 rw1c type(lostmem_dss_mem_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RET_RST signal)"; lostcontext_dff 1 rw1c type(lostmem_dss_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RST signal)"; }; };