/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_cam_cm2.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_cam_cm2 msbfirst ( addr base ) "" {
    

    constants clkactivity_fdif_fclk_status width(1) "" {
        CLKACTIVITY_FDIF_FCLK_0_r = 0 "Corresponding clock is definitely gated";
        CLKACTIVITY_FDIF_FCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
    };

    constants clktrctrl_status width(2) "" {
        CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
        CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
        CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
        CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
    };
    
    register cm_cam_clkstctrl addr(base, 0x0) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
        _ 21 mbz;
        clkactivity_fdif_fclk 1 ro type(clkactivity_fdif_fclk_status) "This field indicates the state of the FDIF_FCLK clock input of the domain. [warm reset insensitive]";
        clkactivity_cam_phy_ctrl_clk 1 ro type(clkactivity_fdif_fclk_status) "This field indicates the state of the CAM_PHY_CTRL_CLK clock input of the domain. [warm reset insensitive]";
        clkactivity_iss_clk 1 ro type(clkactivity_fdif_fclk_status) "This field indicates the state of the ISS_CLK clock input of the domain. [warm reset insensitive]";
        _ 6 mbz;
        clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the CAM clock domain.";
    };

    constants l3_2_statdep_status width(1) "" {
        L3_2_STATDEP_1_r = 1 "Dependency is enabled";
    };

    constants l3_1_statdep_status width(1) "" {
        L3_1_STATDEP_0 = 0 "Dependency is disabled";
        L3_1_STATDEP_1 = 1 "Dependency is enabled";
    };
    
    register cm_cam_staticdep addr(base, 0x4) "This register controls the static domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having system initiator(s)." {
        _ 25 mbz;
        l3_2_statdep 1 ro type(l3_2_statdep_status) "Static dependency towards L3_2 clock domain";
        l3_1_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards L3_1 clock domain";
        memif_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards MEMIF clock domain";
        _ 1 mbz;
        ivahd_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards IVAHD clock domain";
        _ 2 mbz;
    };
    
    register cm_cam_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." {
        _ 25 mbz;
        l3_2_dyndep 1 ro type(l3_1_statdep_status) "Dynamic dependency towards L3_2 clock domain";
        _ 6 mbz;
    };

    constants stbyst_status width(1) "" {
        STBYST_0_r = 0 "Module is functional (not in standby)";
        STBYST_1_r = 1 "Module is in standby";
    };

    constants idlest_status width(2) "" {
        IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
        IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
        IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
        IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
    };

    constants optfclken_ctrlclk_status width(1) "" {
        OPTFCLKEN_CTRLCLK_0 = 0 "Optional functional clock is disabled";
        OPTFCLKEN_CTRLCLK_1 = 1 "Optional functional clock is enabled";
    };

    constants modulemode_status width(2) "" {
        MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
        MODULEMODE_1_r = 1 "Reserved";
        MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
        MODULEMODE_3_r = 3 "Reserved";
    };
    
    register cm_cam_iss_clkctrl addr(base, 0x20) "This register manages the ISS clocks." {
        _ 13 mbz;
        stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 7 mbz;
        optfclken_ctrlclk 1 rw type(optfclken_ctrlclk_status) "Optional functional clock control for CAM_PHY_CTRL_GCLK 96Mhz clock.";
        _ 6 mbz;
        modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
    };

    constants clksel_fclk_status width(2) "" {
        CLKSEL_FCLK_0 = 0 "FDIF_FCLK is divide by 1 of FUNC_128_CLK, to be used for OPP100";
        CLKSEL_FCLK_1 = 1 "FDIF_FCLK is divide by 2 of FUNC_128_CLK, to be used for OPP50";
        CLKSEL_FCLK_2 = 2 "FDIF_FCLK is divide by 4 of FUNC_128_CLK";
        CLKSEL_FCLK_3 = 3 "Reserved";
    };
    
    register cm_cam_fdif_clkctrl addr(base, 0x28) "This register manages the FDIF clocks." {
        _ 6 mbz;
        clksel_fclk 2 rw type(clksel_fclk_status) "Select the ration of FDIF_FCLK to FUNC_128M_CLK";
        _ 5 mbz;
        stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
    };
};