/*
 * Copyright (c) 2007 - 2018, ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
 */

/*
 * hpet.dev
 *
 * DESCRIPTION: Intel 631xESB/632xESB I/O Controller Hub --
 *              High-Precision Event Timer Registers
 *
 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
 * Datasheet", chapter 26, "High-Precision Event Timer Registers".
 * See also, Intel's "IA-PC HPET (High Precision Event Timers)
 * Specification", Revision 1.0a, October 2004. 
 */
 
 // device device_name leastSignBitFirst 
device hpet lsbfirst ( addr base ) "High-Precision Event Timer" {
    // 26.1.1
    register gcap_id ro addr(base, 0x0) "General Capabilities and Identification" {
        rev_id            8    "Revision Identification";
        num_tim_cap       5    "Number of Timers";
        count_size_cap    1    "Counter Size";
        _                 1    mbz;
        leg_rt_cap        1    "Legacy Replacement Rout Capable";
        vendor_id_cap         16   "Vendor ID";
        counter_clk_per_cap   32   "Main Counter Tick Period";
    };
    
    // 26.1.2 register name attribute space(, ) "description"
    
    register gen_conf rw addr(base, 0x10) "General Configuration" {
        enable_cnf  1          "Overall Enable";
        leg_rt_cnf  1          "Legacy Replacement Rout";
        _          62           mbz;
    };

    // 26.1.3 
    register gintr_sta rw addr(base, 0x20) "General Interrupt Status" {
        t00_int_sts  1      "Timer 0 interrupt active";
        t01_int_sts  1      "Timer 1 interrupt active";
        t02_int_sts  1      "Timer 2 interrupt active";
        _        61     mbz;
    };

    // 26.1.4
    register main_cnt rw addr(base, 0xf0) "Main Counter Value" type(uint64);
    
    // 26.1.5
    regtype tim_conf "Timer Configuration and Capabilities" {
        _                        1      mbz;
        timer_int_type_cnf       1      "Timer Interrupt Type (0:edge-triggered , 1:level-triggered)";
        timer_int_enb_cnf        1      "Timer Interrupt Enable";
        timer_type_cnf           1      "Timer Type (0: non-periodic , 1:periodic)";
        timer_per_int_cap        1      "Periodic Interrupt Capability";
        timer_size_cap           1      "Timer Size (0:32 bits , 1:64 bits)";
        timer_val_set_cnf        1      "Timer Value Set (for periodic mode)";
        _                        1      mbz;
        timer_32mode_cnf         1      "Timer 32-bit mode (1 so that 64 behaves as 32)";
        timer_int_rout_cnf       5      "Interrupt Route (indicates routing to I/O apic)";
        timer_fsb_enb_cnf        1      "FSB Interrupt Enable"; 
        timer_fsb_int_delv_cap   1      "FSB Interrupt Delivery (1: FSB is supported)"; 
        _                        16     mbz;
        timer_int_rout_cap       32     "Interrupt Routing Capability (To which interrupts can the I/O Apic be routed)";    
    };
    

    regtype tim_fsb_int_route "Timer FSB Interrupt Route"{
        timer_fsb_int_val        32 "Timer FSB Interrupt Value";
        timer_fsb_int_addr       32 "Timer FSB Interrupt Address";
    };

    regarray timers_config_reg rw addr(base,0x100) [32 ; 0x20]
    "Timer N Configuration Register" type(tim_conf);

    regarray timers_comparator_reg rw addr(base,0x108) [32 ; 0x20]
    "Timer N Comparator Value Register" type(uint64);

    regarray timers_fsb_int_route_reg rw addr(base,0x110) [32 ; 0x20]
    "Timer N FSB Interrupt Route" type(tim_fsb_int_route);
};
