/*
 * Copyright (c) 2018, ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
 */

/*
 * pci_e1000_msix_cap.dev
 *
 * DESCRIPTION: PCI E1000 MSI-X Capability. The e1k uses a non-standard
 * PCI capabality to describe the MSI-X functionality.
 * 
 * Source: Intel 82574L GBE Controller Familiy Datasheet
 */

device pci_e1000_msix_cap lsbfirst ( addr base ) "PCI E1000 MSI-X Capability" {

  // 9.1.5
  register hdr rw addr(base, 0x00 ) "Capabilities Header" {
    id	   8   "Capability ID";
    next   8   "Next Pointer";
    tblsize   11  "Message Control - Table Size";
    _   3  mbz;
    fm    1  "Function Mask";
    en    1 "MSI-X Enable";
  };

 register msg_upper_addr rw addr(base, 0x04) "Message Upper Address" type(uint32);

 register tbl_location ro addr(base, 0x08) "MSI-X Table Location" {
    bir     3   "Base Address Register Index";
    offset  29  "Table offset";
 };

};
