/*
 * Copyright (c) 2017 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * NOTE: This file has been automatically generated based on the XML files
 * provided by ARM.
 *
 * Download from:
 * https://developer.arm.com/products/architecture/a-profile/exploration-tools
 *
 * Based on version: SysReg_v82A_xml-00bet3.1.tar.gz
 */

/* Source: AArch64-osdlr_el1.xml */
ARMV8_SYSREG_RW(OSDLR_EL1,S3_0_C1_C3_4,32)
/* Source: AArch64-contextidr_el1.xml */
ARMV8_SYSREG_RW(CONTEXTIDR_EL1,S3_0_C13_C0_1,32)
/* Source: AArch64-tpidr_el0.xml */
ARMV8_SYSREG_RW(TPIDR_EL0,S3_3_C13_C0_2,64)
/* Source: AArch64-cntvoff_el2.xml */
ARMV8_SYSREG_RW(CNTVOFF_EL2,S3_4_C14_C0_3,64)
/* Source: AArch64-rmr_el1.xml */
ARMV8_SYSREG_RW(RMR_EL1,S3_0_C12_C0_2,32)
/* Source: AArch64-ifsr32_el2.xml */
ARMV8_SYSREG_RW(IFSR32_EL2,S3_4_C5_C0_1,32)
/* Source: AArch64-far_el2.xml */
ARMV8_SYSREG_RW(FAR_EL2,S3_4_C6_C0_0,64)
/* Source: AArch64-cnthp_tval_el2.xml */
ARMV8_SYSREG_RW(CNTHP_TVAL_EL2,S3_4_C14_C2_0,32)
/* Source: AArch64-hstr_el2.xml */
ARMV8_SYSREG_RW(HSTR_EL2,S3_4_C1_C1_3,32)
/* Source: AArch64-icc_ctlr_el1.xml */
ARMV8_SYSREG_RW(ICC_CTLR_EL1,S3_0_C12_C12_4,32)
/* Source: AArch64-ich_ap0rn_el2.xml */
ARMV8_SYSREG_RW(ICH_AP0R0_EL2,S3_4_C12_C8_0,32)
ARMV8_SYSREG_RW(ICH_AP0R1_EL2,S3_4_C12_C8_1,32)
ARMV8_SYSREG_RW(ICH_AP0R2_EL2,S3_4_C12_C8_2,32)
/* Source: AArch64-cptr_el2.xml */
ARMV8_SYSREG_RW(CPTR_EL2,S3_4_C1_C1_2,32)
/* Source: AArch64-dbgdtr_el0.xml */
ARMV8_SYSREG_RW(DBGDTR_EL0,S3_3_C0_C4_0,64)
/* Source: AArch64-mdrar_el1.xml */
ARMV8_SYSREG_RW(MDRAR_EL1,S3_0_C1_C0_0,64)
/* Source: AArch64-afsr0_el3.xml */
ARMV8_SYSREG_RW(AFSR0_EL3,S3_6_C5_C1_0,32)
/* Source: AArch64-amair_el2.xml */
ARMV8_SYSREG_RW(AMAIR_EL2,S3_4_C10_C3_0,64)
/* Source: AArch64-far_el1.xml */
ARMV8_SYSREG_RW(FAR_EL1,S3_0_C6_C0_0,64)
/* Source: AArch64-id_isar4_el1.xml */
ARMV8_SYSREG_RW(ID_ISAR4_EL1,S3_0_C0_C2_4,32)
/* Source: AArch64-dacr32_el2.xml */
ARMV8_SYSREG_RW(DACR32_EL2,S3_4_C3_C0_0,32)
/* Source: AArch64-rvbar_el2.xml */
ARMV8_SYSREG_RW(RVBAR_EL2,S3_4_C12_C0_1,64)
/* Source: AArch64-dbgclaimclr_el1.xml */
ARMV8_SYSREG_RW(DBGCLAIMCLR_EL1,S3_0_C7_C9_6,32)
/* Source: AArch64-lorc_el1.xml */
ARMV8_SYSREG_RW(LORC_EL1,S3_0_C10_C4_3,64)
/* Source: AArch64-mair_el2.xml */
ARMV8_SYSREG_RW(MAIR_EL2,S3_4_C10_C2_0,64)
/* Source: AArch64-sctlr_el1.xml */
ARMV8_SYSREG_RW(SCTLR_EL1,S3_0_C1_C0_0,32)
/* Source: AArch64-cntpct_el0.xml */
ARMV8_SYSREG_RW(CNTPCT_EL0,S3_3_C14_C0_1,64)
/* Source: AArch64-mdcr_el2.xml */
ARMV8_SYSREG_RW(MDCR_EL2,S3_4_C1_C1_1,32)
/* Source: AArch64-oseccr_el1.xml */
ARMV8_SYSREG_RW(OSECCR_EL1,S3_0_C0_C6_2,32)
/* Source: AArch64-spsr_und.xml */
ARMV8_SYSREG_RW(SPSR_und,S3_4_C4_C3_2,32)
/* Source: AArch64-id_isar3_el1.xml */
ARMV8_SYSREG_RW(ID_ISAR3_EL1,S3_0_C0_C2_3,32)
/* Source: AArch64-icc_ctlr_el3.xml */
ARMV8_SYSREG_RW(ICC_CTLR_EL3,S3_6_C12_C12_4,32)
/* Source: AArch64-icc_sgi1r_el1.xml */
ARMV8_SYSREG_RW(ICC_SGI1R_EL1,S3_0_C12_C11_5,64)
/* Source: AArch64-contextidr_el2.xml */
ARMV8_SYSREG_RW(CONTEXTIDR_EL2,S3_4_C13_C0_1,32)
/* Source: AArch64-id_aa64mmfr1_el1.xml */
ARMV8_SYSREG_RW(ID_AA64MMFR1_EL1,S3_0_C0_C7_1,64)
/* Source: AArch64-pmintenclr_el1.xml */
ARMV8_SYSREG_RW(PMINTENCLR_EL1,S3_0_C9_C14_2,32)
/* Source: AArch64-tcr_el1.xml */
ARMV8_SYSREG_RW(TCR_EL1,S3_0_C2_C0_2,64)
/* Source: AArch64-tcr_el3.xml */
ARMV8_SYSREG_RW(TCR_EL3,S3_6_C2_C0_2,32)
/* Source: AArch64-icc_iar0_el1.xml */
ARMV8_SYSREG_RW(ICC_IAR0_EL1,S3_0_C12_C8_0,32)
/* Source: AArch64-actlr_el3.xml */
ARMV8_SYSREG_RW(ACTLR_EL3,S3_6_C1_C0_1,64)
/* Source: AArch64-id_mmfr4_el1.xml */
ARMV8_SYSREG_RW(ID_MMFR4_EL1,S3_0_C0_C2_6,32)
/* Source: AArch64-daif.xml */
ARMV8_SYSREG_RW(DAIF,S3_3_C4_C2_1,32)
/* Source: AArch64-elr_el3.xml */
ARMV8_SYSREG_RW(ELR_EL3,S3_6_C4_C0_1,64)
/* Source: AArch64-dbgprcr_el1.xml */
ARMV8_SYSREG_RW(DBGPRCR_EL1,S3_0_C1_C4_4,32)
/* Source: AArch64-pmuserenr_el0.xml */
ARMV8_SYSREG_RW(PMUSERENR_EL0,S3_3_C9_C14_0,32)
/* Source: AArch64-cntps_tval_el1.xml */
ARMV8_SYSREG_RW(CNTPS_TVAL_EL1,S3_7_C14_C2_0,32)
/* Source: AArch64-pmselr_el0.xml */
ARMV8_SYSREG_RW(PMSELR_EL0,S3_3_C9_C12_5,32)
/* Source: AArch64-rmr_el2.xml */
ARMV8_SYSREG_RW(RMR_EL2,S3_4_C12_C0_2,32)
/* Source: AArch64-spsr_el1.xml */
ARMV8_SYSREG_RW(SPSR_EL1,S3_0_C4_C0_0,32)
/* Source: AArch64-id_aa64pfr1_el1.xml */
ARMV8_SYSREG_RW(ID_AA64PFR1_EL1,S3_0_C0_C4_1,64)
/* Source: AArch64-pmswinc_el0.xml */
ARMV8_SYSREG_RW(PMSWINC_EL0,S3_3_C9_C12_4,32)
/* Source: AArch64-osdtrtx_el1.xml */
ARMV8_SYSREG_RW(OSDTRTX_EL1,S3_0_C0_C3_2,32)
/* Source: AArch64-lorn_el1.xml */
ARMV8_SYSREG_RW(LORN_EL1,S3_0_C10_C4_2,64)
/* Source: AArch64-dbgvcr32_el2.xml */
ARMV8_SYSREG_RW(DBGVCR32_EL2,S3_4_C0_C7_0,32)
/* Source: AArch64-uao.xml */
ARMV8_SYSREG_RW(UAO,S3_0_C4_C2_4,32)
/* Source: AArch64-spsr_el3.xml */
ARMV8_SYSREG_RW(SPSR_EL3,S3_6_C4_C0_0,32)
/* Source: AArch64-cntkctl_el1.xml */
ARMV8_SYSREG_RW(CNTKCTL_EL1,S3_0_C14_C1_0,32)
/* Source: AArch64-ctr_el0.xml */
ARMV8_SYSREG_RW(CTR_EL0,S3_3_C0_C0_1,32)
/* Source: AArch64-id_aa64mmfr0_el1.xml */
ARMV8_SYSREG_RW(ID_AA64MMFR0_EL1,S3_0_C0_C7_0,64)
/* Source: AArch64-tpidrro_el0.xml */
ARMV8_SYSREG_RW(TPIDRRO_EL0,S3_3_C13_C0_3,64)
/* Source: AArch64-pmevcntrn_el0.xml */
ARMV8_SYSREG_RW(PMEVCNTR0_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR1_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR2_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR3_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR4_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR5_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR6_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR7_EL0,S3_3_C14_C4_0,32)
ARMV8_SYSREG_RW(PMEVCNTR8_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR9_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR10_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR11_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR12_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR13_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR14_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR15_EL0,S3_3_C14_C5_0,32)
ARMV8_SYSREG_RW(PMEVCNTR16_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR17_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR18_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR19_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR20_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR21_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR22_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR23_EL0,S3_3_C14_C6_0,32)
ARMV8_SYSREG_RW(PMEVCNTR24_EL0,S3_3_C14_C7_0,32)
ARMV8_SYSREG_RW(PMEVCNTR25_EL0,S3_3_C14_C7_0,32)
ARMV8_SYSREG_RW(PMEVCNTR26_EL0,S3_3_C14_C7_0,32)
ARMV8_SYSREG_RW(PMEVCNTR27_EL0,S3_3_C14_C7_0,32)
ARMV8_SYSREG_RW(PMEVCNTR28_EL0,S3_3_C14_C7_0,32)
ARMV8_SYSREG_RW(PMEVCNTR29_EL0,S3_3_C14_C7_0,32)
/* Source: AArch64-ich_hcr_el2.xml */
ARMV8_SYSREG_RW(ICH_HCR_EL2,S3_4_C12_C11_0,32)
/* Source: AArch64-icc_igrpen1_el3.xml */
ARMV8_SYSREG_RW(ICC_IGRPEN1_EL3,S3_6_C12_C12_7,32)
/* Source: AArch64-mdcr_el3.xml */
ARMV8_SYSREG_RW(MDCR_EL3,S3_6_C1_C3_1,32)
/* Source: AArch64-tpidr_el2.xml */
ARMV8_SYSREG_RW(TPIDR_EL2,S3_4_C13_C0_2,64)
/* Source: AArch64-spsr_irq.xml */
ARMV8_SYSREG_RW(SPSR_irq,S3_4_C4_C3_0,32)
/* Source: AArch64-icc_hppir0_el1.xml */
ARMV8_SYSREG_RW(ICC_HPPIR0_EL1,S3_0_C12_C8_2,32)
/* Source: AArch64-pmceid0_el0.xml */
ARMV8_SYSREG_RW(PMCEID0_EL0,S3_3_C9_C12_6,64)
/* Source: AArch64-fpsr.xml */
ARMV8_SYSREG_RW(FPSR,S3_3_C4_C4_1,32)
/* Source: AArch64-ich_vmcr_el2.xml */
ARMV8_SYSREG_RW(ICH_VMCR_EL2,S3_4_C12_C11_7,32)
/* Source: AArch64-dlr_el0.xml */
ARMV8_SYSREG_RW(DLR_EL0,S3_3_C4_C5_1,64)
/* Source: AArch64-spsr_abt.xml */
ARMV8_SYSREG_RW(SPSR_abt,S3_4_C4_C3_1,32)
/* Source: AArch64-mvfr0_el1.xml */
ARMV8_SYSREG_RW(MVFR0_EL1,S3_0_C0_C3_0,32)
/* Source: AArch64-hpfar_el2.xml */
ARMV8_SYSREG_RW(HPFAR_EL2,S3_4_C6_C0_4,64)
/* Source: AArch64-id_isar5_el1.xml */
ARMV8_SYSREG_RW(ID_ISAR5_EL1,S3_0_C0_C2_5,32)
/* Source: AArch64-cntps_cval_el1.xml */
ARMV8_SYSREG_RW(CNTPS_CVAL_EL1,S3_7_C14_C2_2,64)
/* Source: AArch64-esr_el1.xml */
ARMV8_SYSREG_RW(ESR_EL1,S3_0_C5_C2_0,32)
/* Source: AArch64-vpidr_el2.xml */
ARMV8_SYSREG_RW(VPIDR_EL2,S3_4_C0_C0_0,32)
/* Source: AArch64-mvfr1_el1.xml */
ARMV8_SYSREG_RW(MVFR1_EL1,S3_0_C0_C3_1,32)
/* Source: AArch64-sp_el2.xml */
ARMV8_SYSREG_RW(SP_EL2,S3_6_C4_C1_0,64)
/* Source: AArch64-ich_vtr_el2.xml */
ARMV8_SYSREG_RW(ICH_VTR_EL2,S3_4_C12_C11_1,32)
/* Source: AArch64-vtcr_el2.xml */
ARMV8_SYSREG_RW(VTCR_EL2,S3_4_C2_C1_2,32)
/* Source: AArch64-vttbr_el2.xml */
ARMV8_SYSREG_RW(VTTBR_EL2,S3_4_C2_C1_0,64)
/* Source: AArch64-pmxevcntr_el0.xml */
ARMV8_SYSREG_RW(PMXEVCNTR_EL0,S3_3_C9_C13_2,32)
/* Source: AArch64-fpcr.xml */
ARMV8_SYSREG_RW(FPCR,S3_3_C4_C4_0,32)
/* Source: AArch64-aidr_el1.xml */
ARMV8_SYSREG_RW(AIDR_EL1,S3_1_C0_C0_7,32)
/* Source: AArch64-cnthv_tval_el2.xml */
ARMV8_SYSREG_RW(CNTHV_TVAL_EL2,S3_4_C14_C3_0,32)
/* Source: AArch64-icc_dir_el1.xml */
ARMV8_SYSREG_RW(ICC_DIR_EL1,S3_0_C12_C11_1,32)
/* Source: AArch64-tcr_el2.xml */
ARMV8_SYSREG_RW(TCR_EL2,S3_4_C2_C0_2,64)
/* Source: AArch64-oslsr_el1.xml */
ARMV8_SYSREG_RW(OSLSR_EL1,S3_0_C1_C1_4,32)
/* Source: AArch64-revidr_el1.xml */
ARMV8_SYSREG_RW(REVIDR_EL1,S3_0_C0_C0_6,32)
/* Source: AArch64-icc_eoir1_el1.xml */
ARMV8_SYSREG_RW(ICC_EOIR1_EL1,S3_0_C12_C12_1,32)
/* Source: AArch64-amair_el3.xml */
ARMV8_SYSREG_RW(AMAIR_EL3,S3_6_C10_C3_0,64)
/* Source: AArch64-spsel.xml */
ARMV8_SYSREG_RW(SPSel,S3_0_C4_C2_0,32)
/* Source: AArch64-id_mmfr0_el1.xml */
ARMV8_SYSREG_RW(ID_MMFR0_EL1,S3_0_C0_C1_4,32)
/* Source: AArch64-icc_ap0rn_el1.xml */
ARMV8_SYSREG_RW(ICC_AP0R0_EL1,S3_0_C12_C8_4,32)
ARMV8_SYSREG_RW(ICC_AP0R1_EL1,S3_0_C12_C8_5,32)
ARMV8_SYSREG_RW(ICC_AP0R2_EL1,S3_0_C12_C8_6,32)
/* Source: AArch64-id_mmfr2_el1.xml */
ARMV8_SYSREG_RW(ID_MMFR2_EL1,S3_0_C0_C1_6,32)
/* Source: AArch64-pmintenset_el1.xml */
ARMV8_SYSREG_RW(PMINTENSET_EL1,S3_0_C9_C14_1,32)
/* Source: AArch64-id_isar0_el1.xml */
ARMV8_SYSREG_RW(ID_ISAR0_EL1,S3_0_C0_C2_0,32)
/* Source: AArch64-currentel.xml */
ARMV8_SYSREG_RW(CurrentEL,S3_0_C4_C2_2,32)
/* Source: AArch64-actlr_el2.xml */
ARMV8_SYSREG_RW(ACTLR_EL2,S3_4_C1_C0_1,64)
/* Source: AArch64-mair_el3.xml */
ARMV8_SYSREG_RW(MAIR_EL3,S3_6_C10_C2_0,64)
/* Source: AArch64-ttbr0_el3.xml */
ARMV8_SYSREG_RW(TTBR0_EL3,S3_6_C2_C0_0,64)
/* Source: AArch64-icc_rpr_el1.xml */
ARMV8_SYSREG_RW(ICC_RPR_EL1,S3_0_C12_C11_3,32)
/* Source: AArch64-icc_sre_el2.xml */
ARMV8_SYSREG_RW(ICC_SRE_EL2,S3_4_C12_C9_5,32)
/* Source: AArch64-elr_el1.xml */
ARMV8_SYSREG_RW(ELR_EL1,S3_0_C4_C0_1,64)
/* Source: AArch64-cnthp_ctl_el2.xml */
ARMV8_SYSREG_RW(CNTHP_CTL_EL2,S3_4_C14_C2_1,32)
/* Source: AArch64-cntps_ctl_el1.xml */
ARMV8_SYSREG_RW(CNTPS_CTL_EL1,S3_7_C14_C2_1,32)
/* Source: AArch64-dbgauthstatus_el1.xml */
ARMV8_SYSREG_RW(DBGAUTHSTATUS_EL1,S3_0_C7_C14_6,32)
/* Source: AArch64-afsr0_el2.xml */
ARMV8_SYSREG_RW(AFSR0_EL2,S3_4_C5_C1_0,32)
/* Source: AArch64-pmxevtyper_el0.xml */
ARMV8_SYSREG_RW(PMXEVTYPER_EL0,S3_3_C9_C13_1,32)
/* Source: AArch64-rmr_el3.xml */
ARMV8_SYSREG_RW(RMR_EL3,S3_6_C12_C0_2,32)
/* Source: AArch64-ich_lrn_el2.xml */
ARMV8_SYSREG_RW(ICH_LR0_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR1_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR2_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR3_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR4_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR5_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR6_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR7_EL2,S3_4_C12_C6_0,64)
ARMV8_SYSREG_RW(ICH_LR8_EL2,S3_4_C12_C7_0,64)
ARMV8_SYSREG_RW(ICH_LR9_EL2,S3_4_C12_C7_0,64)
ARMV8_SYSREG_RW(ICH_LR10_EL2,S3_4_C12_C7_0,64)
ARMV8_SYSREG_RW(ICH_LR11_EL2,S3_4_C12_C7_0,64)
ARMV8_SYSREG_RW(ICH_LR12_EL2,S3_4_C12_C7_0,64)
ARMV8_SYSREG_RW(ICH_LR13_EL2,S3_4_C12_C7_0,64)
ARMV8_SYSREG_RW(ICH_LR14_EL2,S3_4_C12_C7_0,64)
/* Source: AArch64-dbgdtrrx_el0.xml */
ARMV8_SYSREG_RW(DBGDTRRX_EL0,S3_3_C0_C5_0,32)
/* Source: AArch64-icc_eoir0_el1.xml */
ARMV8_SYSREG_RW(ICC_EOIR0_EL1,S3_0_C12_C8_1,32)
/* Source: AArch64-ttbr0_el2.xml */
ARMV8_SYSREG_RW(TTBR0_EL2,S3_4_C2_C0_0,64)
/* Source: AArch64-cnthv_cval_el2.xml */
ARMV8_SYSREG_RW(CNTHV_CVAL_EL2,S3_4_C14_C3_2,64)
/* Source: AArch64-id_aa64dfr1_el1.xml */
ARMV8_SYSREG_RW(ID_AA64DFR1_EL1,S3_0_C0_C5_1,64)
/* Source: AArch64-icc_igrpen0_el1.xml */
ARMV8_SYSREG_RW(ICC_IGRPEN0_EL1,S3_0_C12_C12_6,32)
/* Source: AArch64-tpidr_el3.xml */
ARMV8_SYSREG_RW(TPIDR_EL3,S3_6_C13_C0_2,64)
/* Source: AArch64-pan.xml */
ARMV8_SYSREG_RW(PAN,S3_0_C4_C2_3,32)
/* Source: AArch64-id_isar2_el1.xml */
ARMV8_SYSREG_RW(ID_ISAR2_EL1,S3_0_C0_C2_2,32)
/* Source: AArch64-par_el1.xml */
ARMV8_SYSREG_RW(PAR_EL1,S3_0_C7_C4_0,64)
/* Source: AArch64-id_pfr0_el1.xml */
ARMV8_SYSREG_RW(ID_PFR0_EL1,S3_0_C0_C1_0,32)
/* Source: AArch64-sder32_el3.xml */
ARMV8_SYSREG_RW(SDER_EL3,S3_6_C1_C1_1,32)
/* Source: AArch64-icc_iar1_el1.xml */
ARMV8_SYSREG_RW(ICC_IAR1_EL1,S3_0_C12_C12_0,32)
/* Source: AArch64-mair_el1.xml */
ARMV8_SYSREG_RW(MAIR_EL1,S3_0_C10_C2_0,64)
/* Source: AArch64-ttbr1_el2.xml */
ARMV8_SYSREG_RW(TTBR1_EL2,S3_4_C2_C0_1,64)
/* Source: AArch64-vbar_el1.xml */
ARMV8_SYSREG_RW(VBAR_EL1,S3_0_C12_C0_0,64)
/* Source: AArch64-dbgdtrtx_el0.xml */
ARMV8_SYSREG_RW(DBGDTRTX_EL0,S3_3_C0_C5_0,32)
/* Source: AArch64-esr_el3.xml */
ARMV8_SYSREG_RW(ESR_EL3,S3_6_C5_C2_0,32)
/* Source: AArch64-vbar_el3.xml */
ARMV8_SYSREG_RW(VBAR_EL3,S3_6_C12_C0_0,64)
/* Source: AArch64-cntv_ctl_el0.xml */
ARMV8_SYSREG_RW(CNTV_CTL_EL02,S3_5_C14_C3_1,32)
/* Source: AArch64-far_el3.xml */
ARMV8_SYSREG_RW(FAR_EL3,S3_6_C6_C0_0,64)
/* Source: AArch64-scr_el3.xml */
ARMV8_SYSREG_RW(SCR_EL3,S3_6_C1_C1_0,32)
/* Source: AArch64-actlr_el1.xml */
ARMV8_SYSREG_RW(ACTLR_EL1,S3_0_C1_C0_1,64)
/* Source: AArch64-lorid_el1.xml */
ARMV8_SYSREG_RW(LORID_EL1,S3_0_C10_C4_7,64)
/* Source: AArch64-id_afr0_el1.xml */
ARMV8_SYSREG_RW(ID_AFR0_EL1,S3_0_C0_C1_3,32)
/* Source: AArch64-afsr1_el2.xml */
ARMV8_SYSREG_RW(AFSR1_EL2,S3_4_C5_C1_1,32)
/* Source: AArch64-sctlr_el3.xml */
ARMV8_SYSREG_RW(SCTLR_EL3,S3_6_C1_C0_0,32)
/* Source: AArch64-icc_sgi0r_el1.xml */
ARMV8_SYSREG_RW(ICC_SGI0R_EL1,S3_0_C12_C11_7,64)
/* Source: AArch64-icc_bpr0_el1.xml */
ARMV8_SYSREG_RW(ICC_BPR0_EL1,S3_0_C12_C8_3,32)
/* Source: AArch64-pmevtypern_el0.xml */
ARMV8_SYSREG_RW(PMEVTYPER0_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER1_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER2_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER3_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER4_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER5_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER6_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER7_EL0,S3_3_C14_C12_0,32)
ARMV8_SYSREG_RW(PMEVTYPER8_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER9_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER10_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER11_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER12_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER13_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER14_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER15_EL0,S3_3_C14_C13_0,32)
ARMV8_SYSREG_RW(PMEVTYPER16_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER17_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER18_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER19_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER20_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER21_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER22_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER23_EL0,S3_3_C14_C14_0,32)
ARMV8_SYSREG_RW(PMEVTYPER24_EL0,S3_3_C14_C15_0,32)
ARMV8_SYSREG_RW(PMEVTYPER25_EL0,S3_3_C14_C15_0,32)
ARMV8_SYSREG_RW(PMEVTYPER26_EL0,S3_3_C14_C15_0,32)
ARMV8_SYSREG_RW(PMEVTYPER27_EL0,S3_3_C14_C15_0,32)
ARMV8_SYSREG_RW(PMEVTYPER28_EL0,S3_3_C14_C15_0,32)
ARMV8_SYSREG_RW(PMEVTYPER29_EL0,S3_3_C14_C15_0,32)
/* Source: AArch64-icc_igrpen1_el1.xml */
ARMV8_SYSREG_RW(ICC_IGRPEN1_EL1,S3_0_C12_C12_7,32)
/* Source: AArch64-spsr_fiq.xml */
ARMV8_SYSREG_RW(SPSR_fiq,S3_4_C4_C3_3,32)
/* Source: AArch64-id_isar1_el1.xml */
ARMV8_SYSREG_RW(ID_ISAR1_EL1,S3_0_C0_C2_1,32)
/* Source: AArch64-dspsr_el0.xml */
ARMV8_SYSREG_RW(DSPSR_EL0,S3_3_C4_C5_0,32)
/* Source: AArch64-id_aa64isar0_el1.xml */
ARMV8_SYSREG_RW(ID_AA64ISAR0_EL1,S3_0_C0_C6_0,64)
/* Source: AArch64-id_aa64pfr0_el1.xml */
ARMV8_SYSREG_RW(ID_AA64PFR0_EL1,S3_0_C0_C4_0,64)
/* Source: AArch64-rvbar_el1.xml */
ARMV8_SYSREG_RW(RVBAR_EL1,S3_0_C12_C0_1,64)
/* Source: AArch64-dczid_el0.xml */
ARMV8_SYSREG_RW(DCZID_EL0,S3_3_C0_C0_7,32)
/* Source: AArch64-id_dfr0_el1.xml */
ARMV8_SYSREG_RW(ID_DFR0_EL1,S3_0_C0_C1_2,32)
/* Source: AArch64-spsr_el2.xml */
ARMV8_SYSREG_RW(SPSR_EL2,S3_4_C4_C0_0,32)
/* Source: AArch64-mdccsr_el0.xml */
ARMV8_SYSREG_RW(MDCCSR_EL0,S3_3_C0_C1_0,32)
/* Source: AArch64-ttbr0_el1.xml */
ARMV8_SYSREG_RW(TTBR0_EL1,S3_0_C2_C0_0,64)
/* Source: AArch64-pmceid1_el0.xml */
ARMV8_SYSREG_RW(PMCEID1_EL0,S3_3_C9_C12_7,64)
/* Source: AArch64-ich_ap1rn_el2.xml */
ARMV8_SYSREG_RW(ICH_AP1R0_EL2,S3_4_C12_C9_0,32)
ARMV8_SYSREG_RW(ICH_AP1R1_EL2,S3_4_C12_C9_1,32)
ARMV8_SYSREG_RW(ICH_AP1R2_EL2,S3_4_C12_C9_2,32)
/* Source: AArch64-icc_pmr_el1.xml */
ARMV8_SYSREG_RW(ICC_PMR_EL1,S3_0_C4_C6_0,32)
/* Source: AArch64-hacr_el2.xml */
ARMV8_SYSREG_RW(HACR_EL2,S3_4_C1_C1_7,32)
/* Source: AArch64-icc_ap1rn_el1.xml */
ARMV8_SYSREG_RW(ICC_AP1R0_EL1,S3_0_C12_C9_0,32)
ARMV8_SYSREG_RW(ICC_AP1R1_EL1,S3_0_C12_C9_1,32)
ARMV8_SYSREG_RW(ICC_AP1R2_EL1,S3_0_C12_C9_2,32)
/* Source: AArch64-ich_misr_el2.xml */
ARMV8_SYSREG_RW(ICH_MISR_EL2,S3_4_C12_C11_2,32)
/* Source: AArch64-id_aa64isar1_el1.xml */
ARMV8_SYSREG_RW(ID_AA64ISAR1_EL1,S3_0_C0_C6_1,64)
/* Source: AArch64-cptr_el3.xml */
ARMV8_SYSREG_RW(CPTR_EL3,S3_6_C1_C1_2,32)
/* Source: AArch64-hcr_el2.xml */
ARMV8_SYSREG_RW(HCR_EL2,S3_4_C1_C1_0,64)
/* Source: AArch64-sctlr_el2.xml */
ARMV8_SYSREG_RW(SCTLR_EL2,S3_4_C1_C0_0,32)
/* Source: AArch64-rvbar_el3.xml */
ARMV8_SYSREG_RW(RVBAR_EL3,S3_6_C12_C0_1,64)
/* Source: AArch64-mpidr_el1.xml */
ARMV8_SYSREG_RW(MPIDR_EL1,S3_0_C0_C0_5,64)
/* Source: AArch64-dbgclaimset_el1.xml */
ARMV8_SYSREG_RW(DBGCLAIMSET_EL1,S3_0_C7_C8_6,32)
/* Source: AArch64-id_aa64dfr0_el1.xml */
ARMV8_SYSREG_RW(ID_AA64DFR0_EL1,S3_0_C0_C5_0,64)
/* Source: AArch64-id_pfr1_el1.xml */
ARMV8_SYSREG_RW(ID_PFR1_EL1,S3_0_C0_C1_1,32)
/* Source: AArch64-vmpidr_el2.xml */
ARMV8_SYSREG_RW(VMPIDR_EL2,S3_4_C0_C0_5,64)
/* Source: AArch64-afsr0_el1.xml */
ARMV8_SYSREG_RW(AFSR0_EL1,S3_0_C5_C1_0,32)
/* Source: AArch64-dbgwvrn_el1.xml */
ARMV8_SYSREG_RW(DBGWVR0_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR1_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR2_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR3_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR4_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR5_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR6_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR7_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR8_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR9_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR10_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR11_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR12_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR13_EL1,S3_0_C0_C0_6,64)
ARMV8_SYSREG_RW(DBGWVR14_EL1,S3_0_C0_C0_6,64)
/* Source: AArch64-pmccntr_el0.xml */
ARMV8_SYSREG_RW(PMCCNTR_EL0,S3_3_C9_C13_0,64)
/* Source: AArch64-nzcv.xml */
ARMV8_SYSREG_RW(NZCV,S3_3_C4_C2_0,32)
/* Source: AArch64-mdccint_el1.xml */
ARMV8_SYSREG_RW(MDCCINT_EL1,S3_0_C0_C2_0,32)
/* Source: AArch64-icc_hppir1_el1.xml */
ARMV8_SYSREG_RW(ICC_HPPIR1_EL1,S3_0_C12_C12_2,32)
/* Source: AArch64-osdtrrx_el1.xml */
ARMV8_SYSREG_RW(OSDTRRX_EL1,S3_0_C0_C0_2,32)
/* Source: AArch64-csselr_el1.xml */
ARMV8_SYSREG_RW(CSSELR_EL1,S3_2_C0_C0_0,32)
/* Source: AArch64-pmcntenset_el0.xml */
ARMV8_SYSREG_RW(PMCNTENSET_EL0,S3_3_C9_C12_1,32)
/* Source: AArch64-afsr1_el3.xml */
ARMV8_SYSREG_RW(AFSR1_EL3,S3_6_C5_C1_1,32)
/* Source: AArch64-cnthp_cval_el2.xml */
ARMV8_SYSREG_RW(CNTHP_CVAL_EL2,S3_4_C14_C2_2,64)
/* Source: AArch64-mvfr2_el1.xml */
ARMV8_SYSREG_RW(MVFR2_EL1,S3_0_C0_C3_2,32)
/* Source: AArch64-id_aa64afr1_el1.xml */
ARMV8_SYSREG_RW(ID_AA64AFR1_EL1,S3_0_C0_C5_5,64)
/* Source: AArch64-oslar_el1.xml */
ARMV8_SYSREG_RW(OSLAR_EL1,S3_0_C1_C0_4,32)
/* Source: AArch64-ttbr1_el1.xml */
ARMV8_SYSREG_RW(TTBR1_EL1,S3_0_C2_C0_1,64)
/* Source: AArch64-fpexc32_el2.xml */
ARMV8_SYSREG_RW(FPEXC32_EL2,S3_4_C5_C3_0,32)
/* Source: AArch64-id_aa64mmfr2_el1.xml */
ARMV8_SYSREG_RW(ID_AA64MMFR2_EL1,S3_0_C0_C7_2,64)
/* Source: AArch64-cntv_cval_el0.xml */
ARMV8_SYSREG_RW(CNTV_CVAL_EL02,S3_5_C14_C3_2,64)
/* Source: AArch64-tpidr_el1.xml */
ARMV8_SYSREG_RW(TPIDR_EL1,S3_0_C13_C0_4,64)
/* Source: AArch64-ich_eisr_el2.xml */
ARMV8_SYSREG_RW(ICH_EISR_EL2,S3_4_C12_C11_3,32)
/* Source: AArch64-ccsidr_el1.xml */
ARMV8_SYSREG_RW(CCSIDR_EL1,S3_1_C0_C0_0,32)
/* Source: AArch64-cntp_ctl_el0.xml */
ARMV8_SYSREG_RW(CNTP_CTL_EL0,S3_3_C14_C2_1,32)
/* Source: AArch64-id_mmfr1_el1.xml */
ARMV8_SYSREG_RW(ID_MMFR1_EL1,S3_0_C0_C1_5,32)
/* Source: AArch64-ich_elrsr_el2.xml */
ARMV8_SYSREG_RW(ICH_ELRSR_EL2,S3_4_C12_C11_5,32)
/* Source: AArch64-sp_el1.xml */
ARMV8_SYSREG_RW(SP_EL1,S3_4_C4_C1_0,64)
/* Source: AArch64-cnthctl_el2.xml */
ARMV8_SYSREG_RW(CNTHCTL_EL2,S3_4_C14_C1_0,32)
/* Source: AArch64-pmcr_el0.xml */
ARMV8_SYSREG_RW(PMCR_EL0,S3_3_C9_C12_0,32)
/* Source: AArch64-dbgwcrn_el1.xml */
ARMV8_SYSREG_RW(DBGWCR0_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR1_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR2_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR3_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR4_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR5_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR6_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR7_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR8_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR9_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR10_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR11_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR12_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR13_EL1,S3_0_C0_C0_7,32)
ARMV8_SYSREG_RW(DBGWCR14_EL1,S3_0_C0_C0_7,32)
/* Source: AArch64-clidr_el1.xml */
ARMV8_SYSREG_RW(CLIDR_EL1,S3_1_C0_C0_1,64)
/* Source: AArch64-sp_el0.xml */
ARMV8_SYSREG_RW(SP_EL0,S3_0_C4_C1_0,64)
/* Source: AArch64-cntfrq_el0.xml */
ARMV8_SYSREG_RW(CNTFRQ_EL0,S3_3_C14_C0_0,32)
/* Source: AArch64-cntp_cval_el0.xml */
ARMV8_SYSREG_RW(CNTP_CVAL_EL0,S3_3_C14_C2_2,64)
/* Source: AArch64-cntvct_el0.xml */
ARMV8_SYSREG_RW(CNTVCT_EL0,S3_3_C14_C0_2,64)
/* Source: AArch64-midr_el1.xml */
ARMV8_SYSREG_RW(MIDR_EL1,S3_0_C0_C0_0,32)
/* Source: AArch64-icc_sre_el3.xml */
ARMV8_SYSREG_RW(ICC_SRE_EL3,S3_6_C12_C12_5,32)
/* Source: AArch64-id_mmfr3_el1.xml */
ARMV8_SYSREG_RW(ID_MMFR3_EL1,S3_0_C0_C1_7,32)
/* Source: AArch64-esr_el2.xml */
ARMV8_SYSREG_RW(ESR_EL2,S3_4_C5_C2_0,32)
/* Source: AArch64-afsr1_el1.xml */
ARMV8_SYSREG_RW(AFSR1_EL1,S3_0_C5_C1_1,32)
/* Source: AArch64-pmcntenclr_el0.xml */
ARMV8_SYSREG_RW(PMCNTENCLR_EL0,S3_3_C9_C12_2,32)
/* Source: AArch64-dbgbcrn_el1.xml */
ARMV8_SYSREG_RW(DBGBCR0_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR1_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR2_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR3_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR4_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR5_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR6_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR7_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR8_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR9_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR10_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR11_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR12_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR13_EL1,S3_0_C0_C0_5,32)
ARMV8_SYSREG_RW(DBGBCR14_EL1,S3_0_C0_C0_5,32)
/* Source: AArch64-isr_el1.xml */
ARMV8_SYSREG_RW(ISR_EL1,S3_0_C12_C1_0,32)
/* Source: AArch64-id_aa64afr0_el1.xml */
ARMV8_SYSREG_RW(ID_AA64AFR0_EL1,S3_0_C0_C5_4,64)
/* Source: AArch64-dbgbvrn_el1.xml */
ARMV8_SYSREG_RW(DBGBVR0_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR1_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR2_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR3_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR4_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR5_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR6_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR7_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR8_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR9_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR10_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR11_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR12_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR13_EL1,S3_0_C0_C0_4,64)
ARMV8_SYSREG_RW(DBGBVR14_EL1,S3_0_C0_C0_4,64)
/* Source: AArch64-amair_el1.xml */
ARMV8_SYSREG_RW(AMAIR_EL1,S3_0_C10_C3_0,64)
/* Source: AArch64-pmccfiltr_el0.xml */
ARMV8_SYSREG_RW(PMCCFILTR_EL0,S3_3_C14_C15_7,32)
/* Source: AArch64-cntv_tval_el0.xml */
ARMV8_SYSREG_RW(CNTV_TVAL_EL02,S3_5_C14_C3_0,32)
/* Source: AArch64-icc_bpr1_el1.xml */
ARMV8_SYSREG_RW(ICC_BPR1_EL1,S3_0_C12_C12_3,32)
/* Source: AArch64-elr_el2.xml */
ARMV8_SYSREG_RW(ELR_EL2,S3_4_C4_C0_1,64)
/* Source: AArch64-icc_sre_el1.xml */
ARMV8_SYSREG_RW(ICC_SRE_EL1,S3_0_C12_C12_5,32)
/* Source: AArch64-lorsa_el1.xml */
ARMV8_SYSREG_RW(LORSA_EL1,S3_0_C10_C4_0,64)
/* Source: AArch64-cntp_tval_el0.xml */
ARMV8_SYSREG_RW(CNTP_TVAL_EL0,S3_3_C14_C2_0,32)
/* Source: AArch64-mdscr_el1.xml */
ARMV8_SYSREG_RW(MDSCR_EL1,S3_0_C0_C2_2,32)
/* Source: AArch64-cnthv_ctl_el2.xml */
ARMV8_SYSREG_RW(CNTHV_CTL_EL2,S3_4_C14_C3_1,32)
/* Source: AArch64-icc_asgi1r_el1.xml */
ARMV8_SYSREG_RW(ICC_ASGI1R_EL1,S3_0_C12_C11_6,64)
/* Source: AArch64-pmovsset_el0.xml */
ARMV8_SYSREG_RW(PMOVSSET_EL0,S3_3_C9_C14_3,32)
/* Source: AArch64-pmovsclr_el0.xml */
ARMV8_SYSREG_RW(PMOVSCLR_EL0,S3_3_C9_C12_3,32)
/* Source: AArch64-lorea_el1.xml */
ARMV8_SYSREG_RW(LOREA_EL1,S3_0_C10_C4_1,64)
/* Source: AArch64-cpacr_el1.xml */
ARMV8_SYSREG_RW(CPACR_EL1,S3_0_C1_C0_2,32)
/* Source: AArch64-vbar_el2.xml */
ARMV8_SYSREG_RW(VBAR_EL2,S3_4_C12_C0_0,64)
