/*
 * Copyright (c) 2015, ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
 */

/*
 * cpuid_amd.dev
 *
 * DESCRIPTION: ia32 CPU ID instruction results
 * 
 * See
 *   AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008
 */

device cpuid_amd lsbfirst () "ia32 / Intel64 CPUID instruction results" {
    
    /*
     *============================================================================
     * Basic Information. 
     *============================================================================
     */
    
    /*
     * CPUID(0, _)
     * --------------------------------------------------------------------------- 
     */
    datatype basic lsbfirst (32) "" {
        max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information";
        vendor0   32 rw "Vendor string part 1";
        vendor2   32 rw "Vendor string part 3";
        vendor1   32 rw "Vendor string part 2";
    };
    
    /*
     * CPUID(1, _)
     * --------------------------------------------------------------------------- 
     */
     
    datatype family lsbfirst(32) "family information in eax register" {        
        stepping    4 rw  "Processor Stepping ID";
        model       4 rw  "Processor Model";
        family      4 rw  "Processor Family";
        _           4 mbz "Reserved";
        extmodel    4 rw "Extended Model ID";
        extfamily   8 rw "Extended Family ID";
        _           4 mbz "Reserved";
    };
    
    datatype miscinfo lsbfirst(32) "info returned in ebx register" {
        brand_idx    8 rw "Brand index";
        cflush_sz    8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)";
        max_log_proc 8 rw "LogicalProcessorCount is the number of cores per processor"; 
        init_apicid  8 rw  "Initial APIC ID";
    };
    
    datatype features lsbfirst(32) "features returned in {ecx, edx}" {
        /* Feature Information (see Figure 3-6 and Table 3-19) */
        sse3        1 rw "Streaming SIMD Extensions 3 (SSE3). ";
        pclmulqdq   1 rw "PCLMULQDQ.";
        dtes64      1 rw "64-bit DS Area";
        monitor     1 rw "MONITOR/MWAIT"; 
        ds_cpl      1 rw "CPL Qualified Debug Store. ";
        vmx         1 rw "Virtual Machine Extensions";
        smx         1 rw "Safer Mode Extensions. ";
        eist        1 rw "Enhanced Intel SpeedStep(r) technology. ";
        tm2         1 rw "Thermal Monitor 2";
        ssse3       1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)";
        cntx_id     1 rw "L1 Context ID. A";
        sdbg        1 rw "IA32_DEBUG_INTERFACE MSR ";
        fma         1 rw "FMA extensions using YMM state.";
        cmpxchg16b  1 rw "CMPXCHG16B Available";
        xtpr        1 rw "xTPR Update Control";
        pdcm        1 rw "Perfmon and Debug Capability";
        _           1 mbz "";
        pcid        1 rw "Process-context identifiers";
        dca         1 rw "ability to prefetch data from a memory mapped device.";
        sse4_1      1 rw "supports SSE4.1. ";
        sse4_2      1 rw "supports SSE4.2. ";
        x2apic      1 rw "supports x2APIC feature";
        movbe       1 rw "supports MOVBE instruction";
        popcnt      1 rw "supports the POPCNT instruction.";
        tsc_one     1 rw "local APIC timer supports one-shot operation ";
        aesni       1 rw " AESNI instruction extensions";
        xsave       1 rw " XSAVE/XRSTOR processor ";
        osxsave     1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction";
        avx         1 rw "AVX instruction extensions";
        f16c        1 rw "16-bit floating-point conversion instructions.";
        rdrand      1 rw "supports RDRAND instruction.";
        _           1 mbz "";
    
        /* Feature Information (see Figure 3-7 and Table 3-20) */
        fpu         1 rw "Floating Point Unit On-Chip";
        vme         1 rw "Virtual 8086 Mode Enhancements";
        de          1 rw "Debugging Extensions. ";
        pse         1 rw "Page Size Extension";
        tsc         1 rw "Time Stamp Counter.";
        msr         1 rw "Model Specific Registers RDMSR and WRMSR Instructions";
        pae         1 rw "Physical Address Extension";
        mce         1 rw "Machine Check Exception. ";
        cx8         1 rw "CMPXCHG8B Instruction.";
        apic        1 rw "APIC On-Chip. ";
        _           1 mbz "";
        sep         1 rw "SYSENTER and SYSEXIT Instructions.";
        mtrr        1 rw "Memory Type Range Registers";
        pge         1 rw "Page Global Bit";
        mca         1 rw "Machine Check Architecture.";
        cmov        1 rw "Conditional Move Instructions";
        pat         1 rw "Page Attribute Table";
        pse36       1 rw "36-Bit Page Size Extension";
        psn         1 rw "Processor Serial Number. ";
        clfsh       1 rw "CLFLUSH Instruction";
        _           1 rw "";
        ds          1 rw "Debug Store";
        acpi        1 rw "Thermal Monitor and Software Controlled Clock Facilities";
        mmx         1 rw "Intel MMX Technology";
        fxsr        1 rw "FXSAVE and FXRSTOR Instructions";
        sse         1 rw "SSE1";
        sse2        1 rw "SSE2";
        ss          1 rw "Self Snoop";
        htt         1 rw "Max APIC IDs reserved field is Valid";
        tm          1 rw "Thermal Monitor";
        _           1 mbz "";
        pbe         1 rw "Pending Break Enable. ";
    };
    
    /*
     * CPUID(0x80000008, _)
     * --------------------------------------------------------------------------- 
     */
    datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" {
        physical    8 rw  "Maximum physical byte address size in bits";
        linear      8 rw  "Maximum linear byte address size in bits. ";  
        guest       8 rw  " maximum guest physical byte address size in bits";
        _           8 mbz "reserved";
    };
    
    datatype apicid lsbfirst(32) "APIC ID Size and Core Count (ecx)" {
        ncores     8 rw  "number of physical cores - 1";
        _          4 mbz "Reserved";  
        apic_sz    4 rw  "APIC ID size";
        _         16 mbz "reserved";
    };    
    
    /*
     * CPUID(0x80000005, _) L1 Cache and TLB Identifiers
     * --------------------------------------------------------------------------- 
     */
    datatype tlb_l1 lsbfirst(32) "" {
        itlb_sz     8 rw  "L2 instruction TLB number of entries for 2/4MB pages ";
        itlb_assoc  8 rw  "L2 instruction TLB associativity for 2/4MB pages ";
        dtlb_sz     8 rw  "L2 data TLB number of entries for 2/4MB pages ";  
        dtlb_assoc  8 rw  "L2 data TLB associativity for 2/4MB pages";
    }; 
     
    datatype l1_2m_tlb lsbfirst(32) "Fn8000_0005_EAX L1 Cache and TLB Identifiers" {
        itlb_sz     8 rw  "L2 instruction TLB number of entries for 2/4MB pages ";
        itlb_assoc  8 rw  "L2 instruction TLB associativity for 2/4MB pages ";
        dtlb_sz     8 rw  "L2 data TLB number of entries for 2/4MB pages ";  
        dtlb_assoc  8 rw  "L2 data TLB associativity for 2/4MB pages";
    }; 
    
    datatype l1_4k_tlb lsbfirst(32) "Fn8000_0005_EBX L1 Cache and TLB Identifiers" {
        itlb_sz     8 rw  "L2 instruction TLB number of entries for 4 KB pages. ";
        itlb_assoc  8 rw  "L2 instruction TLB associativity for 4 KB pages ";
        dtlb_sz     8 rw  "L2 data TLB number of entries for 4 KB pages ";  
        dtlb_assoc  8 rw  "L2 data TLB associativity for 4 KB pages";
    };  

    datatype l1_dcache lsbfirst(32) " Fn8000_0005_ECX L1 Cache and TLB Identifiers" {
        linesize      8 rw  "L1 cache line size in bytes. ";
        lines_per_tag 8 rw  "L1 cache lines per tag. ";
        assoc         8 rw  "L1 cache associativity. See Table 4.";
        size          8 rw  "L1 cache size in KB.";
    };
    
    datatype l1_icache lsbfirst(32) "Fn8000_0005_EDX L1 Cache and TLB Identifiers" {
        linesize      8 rw  "L1 cache line size in bytes. ";
        lines_per_tag 8 rw  "L1 cache lines per tag. ";
        assoc         8 rw  "L1 cache associativity. See Table 4.";  
        size          8 rw  "L1 cache size in KB.";
    };       
    
    /*
     * CPUID(0x80000006, _) TLB and L2/L3 cache information
     * --------------------------------------------------------------------------- 
     */
          
     constants cache_assoc "AMD cache associativity values" {
        cache_assoc_disabled = 0x0 "";
        cache_assoc_direct   = 0x1 "";
        cache_assoc_2way     = 0x2 "";
        cache_assoc_4way     = 0x4 "";
        cache_assoc_8way     = 0x6 "";  
        cache_assoc_16way    = 0x8 ""; 
        cache_assoc_32way    = 0xa "";
        cache_assoc_48way    = 0xb "";
        cache_assoc_64way    = 0xc "";
        cache_assoc_96way    = 0xd "";
        cache_assoc_128way   = 0xe ""; 
        cache_assoc_fully    = 0xf "";
     };
    
    datatype tlb_l2 lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" {
        itlb_sz    12 rw  "L2 instruction TLB number of entries for 2/4MB pages ";
        itlb_assoc  4 rw  "L2 instruction TLB associativity for 2/4MB pages ";
        dtlb_sz    12 rw  "L2 data TLB number of entries for 2/4MB pages ";  
        dtlb_assoc  4 rw  "L2 data TLB associativity for 2/4MB pages";
    }; 
     
    datatype l2_2m_tlb lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" {
        itlb_sz    12 rw  "L2 instruction TLB number of entries for 2/4MB pages ";
        itlb_assoc  4 rw  "L2 instruction TLB associativity for 2/4MB pages ";
        dtlb_sz    12 rw  "L2 data TLB number of entries for 2/4MB pages ";  
        dtlb_assoc  4 rw  "L2 data TLB associativity for 2/4MB pages";
    }; 
     
    datatype l2_4k_tlb lsbfirst(32) " Fn8000_0006_EBX L2 TLB Identifiers" {
        itlb_sz    12 rw  "L2 instruction TLB number of entries for 4 KB pages. ";
        itlb_assoc  4 rw  "L2 instruction TLB associativity for 4 KB pages ";
        dtlb_sz    12 rw  "L2 data TLB number of entries for 4 KB pages ";
        dtlb_assoc  4 rw  "L2 data TLB associativity for 4 KB pages";
    };      
     
    datatype l2_cache lsbfirst(32) "Fn8000_0006_ECX L2 Cache Identifiers" {
        linesize      8 rw  "L2 cache line size in bytes. ";
        lines_per_tag 4 rw  "L2 cache lines per tag. ";
        assoc         4 rw  "L2 cache associativity. See Table 4.";  
        size         16 rw  "L2 cache size in KB.";
    };     
     
     
    datatype l3_cache lsbfirst(32) "Fn8000_0006_EDX L3 Cache Identifiers" {
        linesize      8 rw  "L3 cache line size in bytes. ";
        lines_per_tag 4 rw  "L3 cache lines per tag. ";
        assoc         4 rw  "L3 cache associativity. See Table 4.";  
        _             2 mbz "Reserved";
        size         14 rw  "Specifies the L3 cache size in 512kb blocks";
    };       
    
    /*
     * CPUID(0x80000019, _) TLB for 1G Pages
     * --------------------------------------------------------------------------- 
     */
    datatype tlb_1g_l1 lsbfirst(32) "TLB 1GB Page Identifiers eax" {
        itlb_sz     12 "L1 instruction TLB number of entries for 1 GB pages";
        itlb_assoc   4 "L1 instruction TLB associativity for 1 GB pages. See Table 4";
        dtlb_sz     12 "L1 data TLB number of entries for 1 GB pages";
        dtlb_assoc   4 "L1 data TLB associativity for 1 GB pages. See Table 4.";
    };    
    
    datatype tlb_1g_l2 lsbfirst(32) "TLB 1GB Page Identifiers ebx" {
        itlb_sz     12 "L2 instruction TLB number of entries for 1 GB pages";
        itlb_assoc   4 "L2 instruction TLB associativity for 1 GB pages. See Table 4";
        dtlb_sz     12 "L2 data TLB number of entries for 1 GB pages";
        dtlb_assoc   4 "L2 data TLB associativity for 1 GB pages. See Table 4.";
    }; 
    
    /*
     * CPUID(0x8000001D, _)
     * --------------------------------------------------------------------------- 
     */
     constants cache_type "AMD Cache Type values" {
        cache_type_null     = 0x0 "No more caches";
        cache_type_data     = 0x1 "data cache";
        cache_type_instr    = 0x2 "Instruction Cache";
        cache_type_unified  = 0x3 "Unified Cache";
     };
     
     /* EAX */
     datatype cache_info_eax lsbfirst (32) "" {
        ctype        5 "Cache Type Field";
        level        3 "Cache Level (starts at 1)";
        selfinit     1 "Self Initializing cache level (does not need SW initialization)";
        fullyassoc   1 "Fully Associative cache";
        _            4 "Reserved";
        num_sharing 12 "number of cores sharing cache - 1";
        _            6 "";
     };
    
    datatype cache_info_ebx lsbfirst (32) "" {
       cachelinesize  12 "cache line size in bytes - 1";
       partitions     10 "cache physical line partitions - 1";
       assoc          10 "cache number of ways - 1";
    };
    
    datatype cache_info_ecx lsbfirst (32) "" {
       num_sets    32 "The number of Sets - 1";
    };
    
    datatype cache_info_edx lsbfirst (32) "" {
       wb_inv     1  "Write-Back Invalidate/Invalidate";
       inclusive  1 "Cache Inclusiveness";
       _         30 "reserved";
    };
     
    /*
     * CPUID(0x8000001E, _) topology extensions
     * --------------------------------------------------------------------------- 
     */     
    datatype ext_apic lsbfirst (32) "register eax" {
       extended_apicid 32  "extended APIC ID";
    };
    
    datatype cuid lsbfirst (32) "Fn8000_001E_EBX Compute Unit Identifiers" {
       cuid    8 "compute unit id";
       ncores  2 "Number of cores per compute unit - 1";
       _      22 "Reserved";
    };
    
    datatype nid lsbfirst (32) "Fn8000_001E_ECX Node Identifiers" {
       nodeid  8 "Specifies the node ID";
       nnodeds 3 "Number of nodes per processor - 1";
       _      21 "Reserved";
    };     
};

    
	    

    
    
	
