/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_iss_top.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_iss_top msbfirst ( addr base ) "" {
    
    
    register iss_hl_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32);

    constants standbymode_status width(2) "" {
        STANDBYMODE_0 = 0 "Force-standby. MStandby is asserted unconditionally.";
        STANDBYMODE_1 = 1 "No-standby. MStandby is never asserted.";
        STANDBYMODE_3 = 3 "Smart-standby";
        STANDBYMODE_2 = 2 "Smart-standby";
    };

    constants idlemode_status width(2) "" {
        IDLEMODE_0 = 0 "Force-idle";
        IDLEMODE_1 = 1 "No-idle";
        IDLEMODE_3 = 3 "Smart-idle";
        IDLEMODE_2 = 2 "Smart-idle";
    };

    constants softreset_status width(1) "" {
        SOFTRESET_0_w = 0 "No action";
        SOFTRESET_1_w = 1 "Initiate software reset";
        SOFTRESET_1_r = 1 "Reset (software or other) ongoing";
        SOFTRESET_0_r = 0 "Reset done, no pending action";
    };
    
    register iss_hl_sysconfig addr(base, 0x10) "Clock management configuration" {
        _ 26 mbz;
        standbymode 2 rw type(standbymode_status) "Master interface power management, standby/Wait control";
        idlemode 2 rw type(idlemode_status) "IDLE protocol configuration";
        _ 1 mbz;
        softreset 1 rw type(softreset_status) "Software reset.";
    };

    constants hs_vs_irq_status width(1) "" {
        HS_VS_IRQ_0_w = 0 "No action";
        HS_VS_IRQ_1_w = 1 "Set event (debug)";
        HS_VS_IRQ_1_r = 1 "Event pending";
        HS_VS_IRQ_0_r = 0 "No event pending";
    };
    
    register iss_hl_irqstatus_raw_i_0 addr(base, 0x20) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_raw_i_1 addr(base, 0x30) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_raw_i_2 addr(base, 0x40) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_raw_i_3 addr(base, 0x50) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_raw_i_4 addr(base, 0x60) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_raw_i_5 addr(base, 0x70) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP.";
    };

    constants hs_vs_irq_status1 width(1) "" {
        HS_VS_IRQ_0_w_6 = 0 "No action";
        HS_VS_IRQ_1_w_6 = 1 "Clear (raw) event";
        HS_VS_IRQ_1_r_6 = 1 "Event pending";
        HS_VS_IRQ_0_r_6 = 0 "No (enabled) event pending";
    };
    
    register iss_hl_irqstatus_i_0 addr(base, 0x24) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_i_1 addr(base, 0x34) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_i_2 addr(base, 0x44) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_i_3 addr(base, 0x54) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_i_4 addr(base, 0x64) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqstatus_i_5 addr(base, 0x74) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP";
        bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine";
        cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer";
        ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver";
        csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b";
        csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP.";
    };

    constants hs_vs_irq_status2 width(1) "" {
        HS_VS_IRQ_0_w_12 = 0 "No action";
        HS_VS_IRQ_1_w_12 = 1 "Enable interrupt";
        HS_VS_IRQ_1_r_12 = 1 "Interrupt enabled";
        HS_VS_IRQ_0_r_12 = 0 "Interrupt disabled (masked)";
    };

    constants ccp2_irq8_status width(1) "" {
        CCP2_IRQ8_0_w = 0 "No action Write 0x1: Enable interrupt";
        CCP2_IRQ8_1_r_12 = 1 "Interrupt enabled Read 0x0: Interrupt disabled (masked)";
    };
    
    register iss_hl_irqenable_set_i_0 addr(base, 0x28) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine";
        cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer";
        ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b";
        csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_set_i_1 addr(base, 0x38) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine";
        cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer";
        ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b";
        csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_set_i_2 addr(base, 0x48) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine";
        cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer";
        ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b";
        csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_set_i_3 addr(base, 0x58) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine";
        cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer";
        ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b";
        csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_set_i_4 addr(base, 0x68) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine";
        cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer";
        ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b";
        csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_set_i_5 addr(base, 0x78) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." {
        _ 14 mbz;
        hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP";
        bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine";
        cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer";
        ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver";
        csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b";
        csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a";
        isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP.";
    };

    constants hs_vs_irq_status3 width(1) "" {
        HS_VS_IRQ_0_w_18 = 0 "No action";
        HS_VS_IRQ_1_w_18 = 1 "Disable interrupt";
        HS_VS_IRQ_1_r_18 = 1 "Interrupt enabled";
        HS_VS_IRQ_0_r_18 = 0 "Interrupt disabled (masked)";
    };
    
    register iss_hl_irqenable_clr_i_0 addr(base, 0x2C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." {
        _ 14 mbz;
        hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE";
        cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF";
        ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b";
        csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a";
        isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_clr_i_1 addr(base, 0x3C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." {
        _ 14 mbz;
        hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE";
        cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF";
        ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b";
        csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a";
        isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_clr_i_2 addr(base, 0x4C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." {
        _ 14 mbz;
        hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE";
        cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF";
        ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b";
        csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a";
        isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_clr_i_3 addr(base, 0x5C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." {
        _ 14 mbz;
        hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE";
        cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF";
        ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b";
        csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a";
        isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_clr_i_4 addr(base, 0x6C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." {
        _ 14 mbz;
        hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE";
        cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF";
        ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b";
        csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a";
        isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
    };
    
    register iss_hl_irqenable_clr_i_5 addr(base, 0x7C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." {
        _ 14 mbz;
        hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field.";
        ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver";
        simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP";
        bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE";
        cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF";
        ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver";
        csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b";
        csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a";
        isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
        isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP.";
    };

    constants iss_clk_div_status width(2) "" {
        ISS_CLK_DIV_0 = 0 "FCLK=CLK CFGCLK=CLK/2";
        ISS_CLK_DIV_1 = 1 "FCLK=CLK/2 CFGCLK=CLK/4";
        ISS_CLK_DIV_3 = 3 "Reserved";
        ISS_CLK_DIV_2 = 2 "FCLK=CLK/4 CFGCLK=CLK/8";
    };

    constants input_sel_status width(2) "" {
        INPUT_SEL_0 = 0 "CSI2-A";
        INPUT_SEL_1 = 1 "CSI2-B";
        INPUT_SEL_2 = 2 "CCP2";
        INPUT_SEL_3 = 3 "Parallel interface";
    };

    constants sync_detect_status width(2) "" {
        SYNC_DETECT_0 = 0 "HS falling edge";
        SYNC_DETECT_1 = 1 "HS raising edge";
        SYNC_DETECT_3 = 3 "VS raising edge";
        SYNC_DETECT_2 = 2 "VS falling edge";
    };
    
    register iss_ctrl addr(base, 0x80) "ISS control register" {
        csi2_b_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CSI2 b write bridge. Note: Tag count must be set to 16 for best performance.";
        csi2_a_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CSI2 a write bridge. Note: Tag count must be set to 16 for best performance.";
        ccp2w_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CCP2 write bridge Note: Tag count must be set to 16 for best performance.";
        ccp2r_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CCP2 read bridge Note: Tag count must be set to 16 for best performance.";
        _ 10 mbz;
        iss_clk_div 2 rw type(iss_clk_div_status) "ISS functional clock division CLK refers to the input clock provided to the ISS. FCLK is the functional clock provided to ISS top level and submodules. CFGCLK is the clock used for the configuration network.";
        input_sel 2 rw type(input_sel_status) "Selects ISP input";
        sync_detect 2 rw type(sync_detect_status) "Chooses among rising and falling edge for the HS_VS_IRQ synchronization event";
    };

    constants vport3_clk_status width(1) "" {
        VPORT3_CLK_0 = 0 "Disabled";
        VPORT3_CLK_1 = 1 "Enabled";
    };

    constants ccp2_status width(1) "" {
        CCP2_0_w = 0 "Request shutdown of the submodule. No effect if the submodule clock is already off.";
        CCP2_1_w = 1 "Request enable of the submodule. No effect if the submodule clock is already on.";
    };
    
    register iss_clkctrl addr(base, 0x84) "ISS clock control register. Use to enable/disable the interface and functional clock of ISS submodules." {
        vport3_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the parallel interface";
        vport2_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the CCP2 protocol engine";
        vport1_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the CSI2_B protocol engine";
        vport0_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the CSI2_A protocol engine";
        _ 23 mbz;
        ccp2 1 wo type(ccp2_status) "CCP2";
        csi2_b 1 wo type(ccp2_status) "CSI2_B";
        csi2_a 1 wo type(ccp2_status) "CSI2_A";
        isp 1 wo type(ccp2_status) "ISP";
        simcop 1 wo type(ccp2_status) "SIMCOP";
    };

    constants ccp2_status1 width(1) "" {
        CCP2_1_r = 1 "The submodule is on.";
        CCP2_0_r = 0 "The submodule is off.";
    };
    
    register iss_clkstat addr(base, 0x88) "ISS clock status register." {
        vport3_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the parallel interface";
        vport2_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the CCP2 protocol engine";
        vport1_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the CSI2_B protocol engine";
        vport0_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the CSI2_A protocol engine";
        _ 23 mbz;
        ccp2 1 ro type(ccp2_status1) "CCP2";
        csi2_b 1 ro type(ccp2_status1) "CSI2_B";
        csi2_a 1 ro type(ccp2_status1) "CSI2_A";
        isp 1 ro type(ccp2_status1) "ISP";
        simcop 1 ro type(ccp2_status1) "SIMCOP";
    };

    constants cbuff_pm_status width(2) "" {
        CBUFF_PM_2_r = 2 "Functional";
        CBUFF_PM_1_r = 1 "Transition";
        CBUFF_PM_0_r = 0 "Idle";
    };

    constants simcop_pm_status width(2) "" {
        SIMCOP_PM_2_r = 2 "Functional";
        SIMCOP_PM_1_r = 1 "Transition";
        SIMCOP_PM_0_r = 0 "Standby";
    };
    
    register iss_pm_status addr(base, 0x8C) "ISS power manager status register. Software could know what modules are in functional or STANDBY/IDLE state. This feature could be particularly useful to debug when ISS does not go into STANDBY mode" {
        _ 18 mbz;
        cbuff_pm 2 ro type(cbuff_pm_status) "Power status of the CBUFF.";
        bte_pm 2 ro type(cbuff_pm_status) "Power status of the BTE.";
        simcop_pm 2 ro type(simcop_pm_status) "Power status of the SIMCOP.";
        isp_pm 2 ro type(simcop_pm_status) "Power status of the ISP.";
        ccp2_pm 2 ro type(simcop_pm_status) "Power status of the CCP2.";
        csi2_b_pm 2 ro type(simcop_pm_status) "Power status of the CSI2 module b";
        csi2_a_pm 2 ro type(simcop_pm_status) "Power status of the CSI2 module a";
    };
};