/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_l3init_prm.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_l3init_prm msbfirst ( addr base ) "" {
    

    constants l3init_bank1_onstate_status width(2) "" {
        L3INIT_BANK1_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON.";
    };

    constants l3init_bank1_retstate_status width(1) "" {
        L3INIT_BANK1_RETSTATE_0_r = 0 "Memory bank is off when the domain is in the RETENTION state.";
    };

    constants lowpowerstatechange_status width(1) "" {
        LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change.";
        LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON.";
    };

    constants logicretstate_status width(1) "" {
        LOGICRETSTATE_0 = 0 "Only retention registers are retained and remaing logic is off when the domain is in RETENTION state.";
        LOGICRETSTATE_1 = 1 "Whole logic is retained when domain is in RETENTION state.";
    };

    constants powerstate_status width(2) "" {
        POWERSTATE_0 = 0 "OFF state";
        POWERSTATE_1 = 1 "RETENTION state";
        POWERSTATE_2 = 2 "INACTIVE state";
        POWERSTATE_3 = 3 "ON State";
    };
    
    register pm_l3init_pwrstctrl addr(base, 0x0) "This register controls the L3INIT power state to reach upon a domain sleep transition" {
        _ 14 mbz;
        l3init_bank1_onstate 2 ro type(l3init_bank1_onstate_status) "L3INIT BANK state when domain is ON.";
        _ 7 mbz;
        l3init_bank1_retstate 1 ro type(l3init_bank1_retstate_status) "L3INIT BANK1 state when domain is RETENTION.";
        _ 3 mbz;
        lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain.";
        _ 1 mbz;
        logicretstate 1 rw type(logicretstate_status) "Logic state when power domain is RETENTION";
        powerstate 2 rw type(powerstate_status) "Power state control";
    };

    constants lastpowerstateentered_status width(2) "" {
        LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE";
        LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE";
        LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION";
        LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF";
    };

    constants intransition_status width(1) "" {
        INTRANSITION_0_r = 0 "No ongoing transition on power domain";
        INTRANSITION_1_r = 1 "Power domain transition is in progress.";
    };

    constants l3init_bank1_statest_status width(2) "" {
        L3INIT_BANK1_STATEST_0_r = 0 "Memory is OFF";
        L3INIT_BANK1_STATEST_1_r = 1 "Reserved";
        L3INIT_BANK1_STATEST_2_r = 2 "Reserved";
        L3INIT_BANK1_STATEST_3_r = 3 "Memory is ON";
    };

    constants logicstatest_status width(1) "" {
        LOGICSTATEST_0_r = 0 "Logic in domain is OFF";
        LOGICSTATEST_1_r = 1 "Logic in domain is ON";
    };

    constants powerstatest_status width(2) "" {
        POWERSTATEST_0_r = 0 "Power domain is OFF";
        POWERSTATEST_1_r = 1 "Power domain is in RETENTION";
        POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE";
        POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE";
    };
    
    register pm_l3init_pwrstst addr(base, 0x4) "This register provides a status on the current L3INIT power domain state. [warm reset insensitive]" {
        _ 6 mbz;
        lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only.";
        _ 3 mbz;
        intransition 1 ro type(intransition_status) "Domain transition status";
        _ 14 mbz;
        l3init_bank1_statest 2 ro type(l3init_bank1_statest_status) "L3INIT BANK1 state status";
        _ 1 mbz;
        logicstatest 1 ro type(logicstatest_status) "Logic state status";
        powerstatest 2 ro type(powerstatest_status) "Current power state status";
    };

    constants wkupdep_mmc1_sdma_status width(1) "" {
        WKUPDEP_MMC1_SDMA_0 = 0 "Dependency is disabled";
        WKUPDEP_MMC1_SDMA_1 = 1 "Dependency is enabled";
    };
    
    register pm_l3init_mmc1_wkdep addr(base, 0x28) "This register controls wakeup dependency based on MMC1 service requests." {
        _ 28 mbz;
        wkupdep_mmc1_sdma 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards SDMA + L3_2 + L4PER domains";
        wkupdep_mmc1_dsp 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards DSP + L3_1 + L3_2 + L4_PER domains";
        wkupdep_mmc1_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards MPU_A3 + L3_2 + L4_PER domains";
        wkupdep_mmc1_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards MPU + L3_1 + L3_2 + L4_PER domains";
    };

    constants lostmem_l3init_bank1_status width(1) "" {
        LOSTMEM_L3INIT_BANK1_0 = 0 "Context has been maintained";
        LOSTMEM_L3INIT_BANK1_1 = 1 "Context has been lost";
    };
    
    register rm_l3init_mmc1_context addr(base, 0x2C) "This register contains dedicated MMC1 context statuses. [warm reset insensitive]" {
        _ 23 mbz;
        lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source.";
        _ 6 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register pm_l3init_mmc2_wkdep addr(base, 0x30) "This register controls wakeup dependency based on MMC2 service requests." {
        _ 28 mbz;
        wkupdep_mmc2_sdma 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards SDMA + L3_2 + L4PER domains";
        wkupdep_mmc2_dsp 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards DSP + L3_1 + L3_2 + L4_PER domains";
        wkupdep_mmc2_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards MPU_A3 + L3_2 + L4_PER domains";
        wkupdep_mmc2_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards MPU + L3_1 + L3_2 + L4_PER domains";
    };
    
    register rm_l3init_mmc2_context addr(base, 0x34) "This register contains dedicated MMC2 context statuses. [warm reset insensitive]" {
        _ 23 mbz;
        lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source.";
        _ 6 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register pm_l3init_hsi_wkdep addr(base, 0x38) "This register controls wakeup dependency based on HSI service requests." {
        _ 23 mbz;
        wkupdep_wgm_hsi_wake_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from modem HSI_WAKE signal towards MPU + L3_1 + L4_CFG domains";
        _ 1 mbz;
        wkupdep_hsi_dsp_dsp 1 ro type(wkupdep_mmc1_sdma_status) "Wakeup dependency from HSI module (softwareakeup_DSP signal) towards DSP + L3_1 + L4_CFG domains";
        _ 4 mbz;
        wkupdep_hsi_mcu_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from HSI module (softwareakeup_MPU signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
        wkupdep_hsi_mcu_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from HSI module (softwareakeup_MPU signal) towards MPU + L3_1 + L4_CFG domains";
    };
    
    register rm_l3init_hsi_context addr(base, 0x3C) "This register contains dedicated HSI context statuses. [warm reset insensitive]" {
        _ 23 mbz;
        lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source.";
        _ 6 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register pm_l3init_hsusbhost_wkdep addr(base, 0x58) "This register controls wakeup dependency based on USB_HOST_HS service requests." {
        _ 30 mbz;
        wkupdep_hsusbhost_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_HS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
        wkupdep_hsusbhost_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_HS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
    };
    
    register rm_l3init_hsusbhost_context addr(base, 0x5C) "This register contains dedicated USB_HOST context statuses. [warm reset insensitive]" {
        _ 30 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register pm_l3init_hsusbotg_wkdep addr(base, 0x60) "This register controls wakeup dependency based on USB_OTG_HS service requests." {
        _ 30 mbz;
        wkupdep_hsusbotg_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_OTG_HS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
        wkupdep_hsusbotg_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_OTG_HS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
    };
    
    register rm_l3init_hsusbotg_context addr(base, 0x64) "This register contains dedicated USB_OTG_HS context statuses. [warm reset insensitive]" {
        _ 23 mbz;
        lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source.";
        _ 6 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register pm_l3init_hsusbtll_wkdep addr(base, 0x68) "This register controls wakeup dependency based on USB_TLL service requests." {
        _ 30 mbz;
        wkupdep_hsusbtll_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_TLL module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
        wkupdep_hsusbtll_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_TLL module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
    };
    
    register rm_l3init_hsusbtll_context addr(base, 0x6C) "This register contains dedicated USB_TLL context statuses. [warm reset insensitive]" {
        _ 30 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register pm_l3init_fsusb_wkdep addr(base, 0xD0) "This register controls wakeup dependency based on USB_HOST_FS service requests." {
        _ 30 mbz;
        wkupdep_fsusb_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_FS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
        wkupdep_fsusb_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_FS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
    };
    
    register rm_l3init_fsusb_context addr(base, 0xD4) "This register contains dedicated USB_HOST_FS context statuses. [warm reset insensitive]" {
        _ 30 mbz;
        lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)";
        _ 1 mbz;
    };
    
    register rm_l3init_usbphy_context addr(base, 0xE4) "This register contains dedicated USBPHY context statuses. [warm reset insensitive]" {
        _ 31 mbz;
        lostcontext_dff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RST signal)";
    };
};