/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_usbfshost.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_usbfshost msbfirst ( addr base ) "" {
    
    
    register hcrevision ro addr(base, 0x0) "OHCI revision number" type(uint32);

    constants hcfs_status width(2) "" {
        HCFS_0 = 0 "HCFS: USB reset";
        HCFS_1 = 1 "HCFS: USB resume";
        HCFS_2 = 2 "HCFS: USB operational";
        HCFS_3 = 3 "HCFS: USB suspend";
    };

    constants ble_status width(1) "" {
        BLE_0 = 0 "The bulk ED list is not processed after the next SOF.";
        BLE_1 = 1 "Enables processing of the bulk ED list in the next frame.";
    };

    constants ie_status width(1) "" {
        IE_0 = 0 "Isochronous EDs are not processed.";
        IE_1 = 1 "Enables processing of isochronous EDs";
    };

    constants ple_status width(1) "" {
        PLE_0 = 0 "Periodic ED lists are not processed after the next frame.";
        PLE_1 = 1 "Enables processing of periodic ED lists in the next frame";
    };

    constants cbsr_status width(2) "" {
        CBSR_0 = 0 "One control ED per bulk ED";
        CBSR_1 = 1 "Two control ED per bulk ED";
        CBSR_2 = 2 "Three control ED per bulk ED";
        CBSR_3 = 3 "Four control ED per bulk ED";
    };
    
    register hccontrol addr(base, 0x4) "HC operating mode register" {
        _ 21 mbz;
        rwe 1 rw "Remote wake-up enable";
        rwc 1 rw "Remote wake up connected.";
        ir 1 rw "Interrupt routing.";
        hcfs 2 rw type(hcfs_status) "Host controller functional state";
        ble 1 rw type(ble_status) "Bulk list processing enable";
        cle 1 rw type(ble_status) "Control list processing enable";
        ie 1 rw type(ie_status) "Isochronous ED processing enabled by host controller driver.";
        ple 1 rw type(ple_status) "Periodic list enable";
        cbsr 2 rw type(cbsr_status) "Control/bulk service ratio. Specifies the ratio between control and bulk EDs processedin a frame.";
    };

    constants hcr_status width(1) "" {
        HCR_0 = 0 "No effect";
        HCR_1 = 1 "USB host controller is reset.";
    };
    
    register hccommandstatus addr(base, 0x8) "HC Command and status" {
        _ 14 mbz;
        soc 2 ro "Scheduling overrun count";
        _ 12 mbz;
        ocr 1 rw "Ownership change request";
        blf 1 rw "Bulk list filled";
        clf 1 rw "Control list filled";
        hcr 1 rw type(hcr_status) "Host controller reset (software reset)Set this bit to initiate a USB host controller reset. This resets most USB host controller OHCI registers. OHCI register accesses must not be attempted until a read of this register returns a 0.";
    };
    
    register hcinterruptstatus addr(base, 0xC) "HC Interrupt status" {
        _ 1 mbz;
        oc 1 ro "Ownership change";
        _ 23 mbz;
        rhsc 1 rw "Root hub status changeWhen 0x1: A root hub status change has occurred.Write 0x0: No effectWrite 0x1: Clears this bit";
        fno 1 rw "Frame number overflowWhen 0x1: A frame number overflow has occurred.Write 0x0: No effectWrite 0x1: Clears this bit";
        ue 1 rw "Unrecoverable error.When 0x1: An unrecoverable error has occurred.Write 0x0: No effectWrite 0x1: Clears this bit";
        rd 1 rw "Resume detected.When 0x1: A downstream device has issued a resume request.Write 0x0: No effectWrite 0x1: Clears this bit";
        sf 1 rw "Start of frame.When 0x1: A SOF has been issued.Write 0x0: No effectWrite 0x1: Clears this bit";
        wdh 1 rw "Write done headWhen 0x1: the USB host controller has updated the HCDONEHEAD register.Write 0x0: No effectWrite 0x1: Clears this bit";
        so 1 rw "Scheduling overrunWhen 0x1: A scheduling overrun has occurred.Write 0x0: No effectWrite 0x1: Clears this bit";
    };
    
    register hcinterruptenable addr(base, 0x10) "HC Interrupt Enable" {
        mie 1 rw "Master interrupt enableWhen 0x1: Allows other enabled OHCI interrupt sources to propagate to the device interrupt controller.When 0x0: OHCI interrupt sources are ignored.Write 0x0: No effectWrite 0x1: Sets this bit";
        oc 1 rw "Ownership change";
        _ 23 mbz;
        rhsc 1 rw "Root hub status changeWhen 0x1 and MIE is 0x1: Allows root hub status change interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: root hub status change interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
        fno 1 rw "Frame number overflow.When 0x1 and MIE is 0x1: Allows FNO interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: FNO interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
        ue 1 rw "Unrecoverable error.When 0x1 and MIE is 0x1: Allows UE interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: UE interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
        rd 1 rw "Resume detected.When 0x1 and MIE is 0x1: Allows RD interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: RD interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
        sf 1 rw "Start of frameWhen 0x1 and MIE is 0x1: Allows SF interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: SF interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
        wdh 1 rw "Write done headWhen 0x1 and MIE is 0x1: Allows WDH interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: WDH interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
        so 1 rw "Scheduling overrun.When 0x1 and MIE is 0x1: Allows SO interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: SO interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit";
    };
    
    register hcinterruptdisable addr(base, 0x14) "HC Interrupt disable" {
        mie 1 rw "Master interrupt enableAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE MIE bit";
        oc 1 rw "Ownership change";
        _ 23 mbz;
        rhsc 1 rw "Root hub status changeAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE RHSC bit";
        fno 1 rw "Frame number overflowAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE FNO bit";
        ue 1 rw "Unrecoverable errorAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE UE bit";
        rd 1 rw "Resume detectedAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE RD bit";
        sf 1 rw "Start of frameAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE SF bit";
        wdh 1 rw "Write done headAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE WDH bit";
        so 1 rw "Scheduling overrunAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE SO bit";
    };
    
    register hchcca addr(base, 0x18) "HC HCCA address register" {
        hcca 24 rw "Physical address of the beginning of the HCCA";
        _ 8 mbz;
    };
    
    register hcperiodcurrented addr(base, 0x1C) "HC Current periodic register" {
        pced 28 ro "Physical address of current ED on the periodic ED list";
        _ 4 mbz;
    };
    
    register hccontrolheaded addr(base, 0x20) "HC head control register" {
        ched 28 rw "Physical address of head ED on the control ED list";
        _ 4 mbz;
    };
    
    register hccontrolcurrented addr(base, 0x24) "HC current control register" {
        cced 28 rw "Physical address of current ED on the control ED list";
        _ 4 mbz;
    };
    
    register hcbulkheaded addr(base, 0x28) "HC head bulk register" {
        bhed 28 rw "Physical address of head ED on the bulk ED list";
        _ 4 mbz;
    };
    
    register hcbulkcurrented addr(base, 0x2C) "HC current bulk register" {
        bced 28 rw "Physical address of current ED on the bulk ED list";
        _ 4 mbz;
    };
    
    register hcdonehead addr(base, 0x30) "HC head done register" {
        dh 28 ro "Physical address of last TD that was added to the done queue";
        _ 4 mbz;
    };
    
    register hcfminterval addr(base, 0x34) "HC Frame Interval register" {
        fit 1 rw "Frame interval toggle";
        fsmps 15 rw "Largest data packet size for full-speed packets, bit times.";
        _ 2 mbz;
        fi 14 rw "Frame intervalNumber of 12-MHz clocks in the USB frame. The nominal value is set to 11,999 to give a 1-ms frame.";
    };
    
    register hcfmremaining addr(base, 0x38) "HC Frame-remaining register" {
        frt 1 ro "Frame remaining toggle";
        _ 17 mbz;
        fr 14 ro "Frame remaining";
    };
    
    register hcfmnumber addr(base, 0x3C) "HC Frame number register" {
        _ 16 mbz;
        fn 16 ro "Frame number";
    };
    
    register hcperiodicstart addr(base, 0x40) "HC Periodic start register" {
        _ 18 mbz;
        ps 14 rw "Periodic startThe host controller driver must program this value to be about 10% less than the frame interval field value so that control and bulk EDs have priority for the first 10% of the frame; then periodic EDs have priority for the remaining 90% of the frame.";
    };
    
    register hclsthreshold addr(base, 0x44) "HC low-speed threshold register" {
        _ 20 mbz;
        lst 12 rw "Low-speed threshold.";
    };

    constants nocp_status width(1) "" {
        NOCP_0 = 0 "Overcurrent status is reported collectively for all downstream ports.";
        NOCP_1 = 1 "the USB host controller does not implement overcurrent protection inputs.";
    };

    constants nps_status width(1) "" {
        NPS_0 = 0 "VBUS power switching is supported, either per-port or all-port switched per the power.";
        NPS_1 = 1 "VBUS power switching is not supported, power is available to all downstream ports.";
    };

    constants psm_status width(1) "" {
        PSM_0 = 0 "Indicates that all ports are powered at the same time";
        PSM_1 = 1 "Individual port power switching is supported";
    };
    
    register hcrhdescriptora addr(base, 0x48) "HC root hub A register" {
        potpg 8 rw "Power-on to power-good timeDefines the minimum length of time (2 ms * POTPG) between the USB host controller turning on power to a downstream port, and when the USB host can access the downstream device.";
        _ 11 mbz;
        nocp 1 rw type(nocp_status) "No overcurrent protection";
        ocpm 1 rw "Overcurrent protection mode";
        dt 1 ro "Device typeAlways reads 0x0: Indicates that the USB host controller implemented is not a compound device";
        nps 1 rw type(nps_status) "No power switching";
        psm 1 rw type(psm_status) "Power switching mode";
        ndp 8 ro "Number of downstream ports.";
    };
    
    register hcrhdescriptorb addr(base, 0x4C) "HC root hub B register" {
        _ 14 mbz;
        ppcm 1 rw "Port power control maskThis bit defines whether downstream port #1 has port power controlled by the global power control. When set. the port power state is only affected by per-port power control. When cleared the port is controlled by the global power switch. This field is not valid if the device is configured to global switch mode.";
        _ 1 mbz;
        _ 14 mbz;
        dr 1 rw "Device removableThis bit defines whether the downstream port has a removable device. When cleared, the attached device is removable. When set, the attached device is not removable. bit 1: Device attached to port #1";
        _ 1 mbz;
    };

    constants oci_status width(1) "" {
        OCI_0_r = 0 "All power operations are normal.";
        OCI_1_r = 1 "An overcurrent condition exists.";
    };
    
    register hcrhstatus addr(base, 0x50) "HC root hub status register" {
        crwe 1 wo "Clear remote wake-up enableWrite 0x0: No effectWrite 0x1: Clears the device remote wake-up enable bit";
        _ 13 mbz;
        ocic 1 rw "Overcurrent indication changeThis bit is automatically set when the overcurrent indicator bit changes.Write 0x0: No effectWrite 0x1: Clears this bit";
        lpsc 1 rw "Local power status changeAlways reads 0x0: The root hub does not support the local power status feature.Write 0x0: No effectWrite 0x1: Sets port power status bits for all ports, if power switching mode is 0. Sets port power status bits for ports with their corresponding port power control mask bits cleared if power switching mode is 1.";
        drwe 1 rw "Device remote wake-up enableEnables a connect status change event as a resume event, causing a USB suspend to USB resume state transition and sets the resume detected interrupt status bit.Read 0x1: Connect status change is a remote wake-up event.Read 0x0: Connect status change is not a remote wake-up event.Write 0x0: No effectWrite 0x1: Sets the device remote wake-up enable bit";
        _ 13 mbz;
        oci 1 ro type(oci_status) "Overcurrent indicator. Reports global overcurrent indication if global overcurrent reporting is selected. If per-port overcurrent protection is implemented, this bit is always 0.";
        lps 1 rw "Local power status.Always reads 0x0Write 0x0: No effectWrite 0x1: When in global power mode (power switching mode = 0), turns off power to all ports. If in per-port power mode (power switching mode = 1), turns of power to those ports whose corresponding port power control mask bit is 0.";
    };
    
    register hcrhportstatus addr(base, 0x54) "HC Port 1 status and control register" {
        _ 11 mbz;
        prsc 1 rw "Port 1 reset status changeThis bit is set when the Port 1 port reset status bit has changed.Write 0x0: No effectWrite 0x1: Clears this bit";
        ocic 1 rw "Port 1 overcurrent indicator changeThis bit is set when the Port 1 port overcurrent indicator has changed.Write 0x0: No effectWrite 0x1: Clears this bit";
        pssc 1 rw "Port 1 suspend status changeThis bit is set when the Port1 port suspend status has changed.Write 0x0: No effectWrite 0x1: Clears this bit";
        pesc 1 rw "Port 1 enable status changeThis bit is set when the Port1 port enable status has changed.Write 0x0: No effectWrite 0x1: Clears this bit";
        csc 1 rw "Port 1 connect status changeThis bit is set when the Port1 port current connect status has changed due to a connect or disconnect event. If current connect status is 0 when a set port reset, set port enable, or set port suspend write occurs, this bit is set.Write 0x0: No effectWrite 0x1: Clears this bitNote: If the DR bit HCRHDESCRIPTORB[1] is set, this bit is set only after a root hub reset to inform the system that the device is attached.";
        _ 6 mbz;
        lsda_cpp 1 rw "Port 1 low-speed device attached/clear port power. This bit is valid only when port 1 current connect status is 1.Read 0x0: A full-speed device is attached to port 1.Read 0x1: A low-speed device is attached to port 1.Write 0x0: No effectWrite 0x1: Clears the port 1 port power status.";
        pps_spp 1 rw "Port 1 port power status/set port power.Read 0x0: Port 1 power is off.Read 0x1: Port 1 power is on.Write 0x0: No effectWrite 0x1: Sets the port 1 port power status bit";
        _ 3 mbz;
        prs_spr 1 rw "Port 1 port reset status/set port reset.Read 0x0: USB reset is not being sent to port 1.Read 0x1: Port 1 is signaling the USB reset.Write 0x0: No effectWrite 0x1: Sets the port 1 port reset status bit and causes the USB host controller to begin signaling USB reset to port 1";
        poci_css 1 rw "Port 1 port overcurrent indicator/clear suspend statusRead 0x0: No port 1 port overcurrent condition has occurred.Read 0x1: A port 1 port overcurrent condition has occurred.Write 0x0: No effectWrite 0x1: When port 1 port suspend status is 1, it causes resume signaling on port 1. When port 1 port suspend status is 0, it has no effect.";
        pss_sps 1 rw "Port 1 port suspend status/set port suspendThis bit is cleared automatically at the end of the USB resume sequence and also at the end of the USB reset sequence.Write 0x0: No effectRead 0x0: Port 1 is not in the USB suspend state.Read 0x1: Port 1 is in the USB suspend state or is in the resume sequence.Write 0x1: If port 1 current connect status is 1, sets the port 1 port suspend status bit and places port 1 in USB suspend state. If current connect status is 0, it sets connect status instead change to inform the USB host controller driver in an attempt to suspend a disconnected port.";
        pes_spe 1 rw "Port 1 port enable status/set port enableThis bit is automatically set at completion of port 1 USB reset, if it was not already set before the USB reset completed, and is automatically set at the end of a USB suspend, if the port was not enabled when the USB resume completed.Read 0x0: Port 1 is not enabled.Read 0x1: Port 1 is enabled.Write 0x0: No effectWrite 0x1: When port 1 current connect status is 1, sets the port 1 port enable status bit. When port 1 current status is 0, it has no effect.";
        ccs_cpe 1 rw "Port 1 current connection status/clear port enableRead 0x0: No USB device is attached to port 1.Read 0x1: Port 1 currently has a USB device attached.Write 0x0: No effectWrite 0x1: Clears the port 1 port enable bitNote: This bit is set to 1 if the DR bit HCRHDESCRIPTORB[1] is set to indicate a nonremovable device on port 1.";
    };
    
    register hcocprev ro addr(base, 0x200) "" type(uint32);
    
    register hcocphwi ro addr(base, 0x204) "Hardware information register, maintains the IP modules hardware configuration. The fields can be set to different values through parameters." type(uint32);
    
    register hcocpsys addr(base, 0x210) "OCP system configuration register holds the OCP power down control fields that controls the clock management." {
        _ 22 mbz;
        applicationstartclock 1 rw "1: RCFG_SUSPEND_O output port is masked and this output port is held low (1'b0)0: RCFG_SUSPEND_O port functions normally, that is, it indicates the SUSPEND mode.";
        simulationscaledown 1 rw "1: Simulation runs in time scaled down mode.0: Simulation runs in real time. NOTE: This bit should not be set to 1 in actual hardware.";
        _ 2 mbz;
        standby_mode 2 rw "Standby mode, controls the way USBFSHOST handles the STANDBY protocol.The application can program this field in the following configurations 2'b00 : Force standby 2'b01: Not supported (No-Standby) 2'b10: Smart standby 2'b11: Smart standby wake up";
        idle_mode 2 rw "The idle mode controls the way USBFSHOST handles the IDLE protocol.The application can program this field in the following configurations 2'b00: Force Idle 2'b01: Not supported (No-Idle) 2'b10: Smart-Idle 2'b11: Smart-Idle wake up";
        soft_reset 1 rw "Setting this bit to 1 resets the entire IP, except for OCP-IDLE, OCP-STANDBY, and OCP-DISCONNECT logic.This bit remains set until the IP comes out of soft reset.";
        _ 1 mbz;
    };
};