/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_cortexa9_prm.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_cortexa9_prm msbfirst ( addr base ) "" {
    

    constants global_warm_rst_status width(1) "" {
        GLOBAL_WARM_RST_0 = 0 "No global warm reset.";
        GLOBAL_WARM_RST_1 = 1 "Global external warm reset has occurred.";
    };

    constants global_cold_rst_status width(1) "" {
        GLOBAL_COLD_RST_0 = 0 "No power-on reset.";
        GLOBAL_COLD_RST_1 = 1 "Power-on reset has occurred.";
    };
    
    register prm_rstst addr(base, 0x0) "This register logs the global reset sources, thus contains information regarding the cold/warm reset events generated by global PRCM. Each bit is set upon release of the domain reset signal. Must be cleared by software." {
        _ 30 mbz;
        global_warm_rst 1 rw1c type(global_warm_rst_status) "Global warm reset event generated by Global PRCM";
        global_cold_rst 1 rw1c type(global_cold_rst_status) "Power-on (cold) reset event generated by global PRCM";
    };
    
    register prm_pscon_count addr(base, 0x4) "Programmable Precharge count for L1Cache. This register is useful to ensure the correct delay between toggles of pscon lines and therefore to avoid Any problem of power switch transitions. The register corresponds to the number of device system clock cycles for the SRAM precharge duration. It means that the local PRCM module waits for PCHARGE_TIME cycles of system clock. The pscon modules belongs to the local PRCM modules and are used to control the power of the CPUx." {
        spareused 4 ro "4 bits consumed for Last Power State Entered";
        spare 20 rw "Spare programmable bits";
        pcharge_time 8 rw "Programmable Precharge count during retention";
    };
};