/*
 * Copyright (c) 2014 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
 */

/*
 * xeon_phi_boot.dev
 *
 * description: register definitions for the Xeon Phi Boot Time Registers
 */

device xeon_phi_boot lsbfirst ( addr sbox_base, addr dbox_base ) "Intel Xeon Phi Boot Registers" {

    /*
     * Protection Level: Ring 0
     * Visibility: Host / Coprocessor
     * Reset Dmain: CSR_RESET, HOT_RESET
     * Register Access: TRM
     */
     
     register flash_ctrl rw addr(sbox_base, 0xAB24) {
        percent    7 "Percentage progress";
        status     4 "Status code";
        command    4 "flash command";
        smc_status 4 "SMC Status";
        _          5 "Reserved";
        cmd_data   7 "Command Data";
        mm_debug   1 "Memory debug";
     }; 

     constants offset width(32) "" {
         address_shift=12;
         address_mask=0xfffff000;
     };

    /*
     * alias for scratch register 2
     */
    register download rw addr(sbox_base, 0xAB28) {
        status       1 "Download status bit";
        apicid       9 "APIC ID to send the boot interrupt";
        _            2 "unused";
        offset      20 "Load offset";         
    };
    
    /*
     * alias for scratch register 3
     */
    register res_size rw addr(sbox_base, 0xAB2C) {
        os 32 "Reserved size";
    };
    
    /*
     * alias for scratch register 5
     */
    register os_size rw addr(sbox_base, 0xAB34) {
        size 32 "Size of the loaded image";
    };
    
    constants mem width(2) "" {
          mem_all    = 0x0;
          mem_half   = 0x1;
          mem_third  = 0x2;
          mem_fourth = 0x3;
    };
    
    register meminfo rw addr(sbox_base, 0xAB20) {
          test_disable  1 "Memtest disable";
          usage         2 "Memory usage";	
          size_kb      29 "Memory size in KB";
    };
    
    register reset rw addr(sbox_base, 0x4010) {
        reset  1 "Perform device rest";
        _     31; 
    };
    
    /*
     * Note: The post codes are represented as a two byte ASCII values  
     */
    constants postcodes width(16) "The Xeon Phi Post codes" {
        postcode_lidt           = 0x3130 "01 LIDT";
        postcode_sboxinit       = 0x3230 "02 SBOX initialization";
        postcode_gddrtop        = 0x3330 "03 Set GDDR Top";
        postcode_memtest        = 0x3430 "04 Begin memory test";
        postcode_e820           = 0x3530 "05 Program E820 table";
        postcode_dbox           = 0x3630 "06 Initialize DBOX";
        postcode_cache          = 0x3930 "09 Enable Cache";    
        postcode_initap         = 0x6230 "0b Pass initialization params to APs";
        postcode_code           = 0x6330 "0c Cache C code";
        postcode_mp             = 0x4530 "0E Program MP table";
        postcode_apwkup         = 0x4630 "0F Wake up APs";
        postcode_apboot         = 0x3031 "10 Wait for APs to boot";
        postcode_sig            = 0x3131 "11 Signal host to download OS";
        postcode_ready          = 0x3231 "12 Wait for download READY";
        postcode_boot           = 0x3331 "13 Signal to boot received";
        postcode_pinfo          = 0x3531 "15 Report platform information";
        postcode_ptable         = 0x3731 "17 Page table setup";
        postcode_memtrain       = 0x3033 "30 Begin memory training";
        postcode_gddrtrain      = 0x3133 "31 GDDR Training to query memory modules";
        postcode_findgddrtrain  = 0x3233 "32 Find GDDR training parameters in flash";
        postcode_mmiotrain      = 0x3333 "33 MMIO training";
        postcode_rcomptrain     = 0x3433 "34 RCOMP training";
        postcode_dcctrain       = 0x3533 "35 DCC disable training";
        postcode_hcktrain       = 0x3633 "36 HCK training";
        postcode_ucodetrain     = 0x3733 "37 UCode Training";
        postcode_vendortrain    = 0x3833 "38 Vendor specific training";
        postcode_addrtrain      = 0x3933 "39 GDDR address training";
        postcode_gddrident      = 0x4133 "3A GDDR memory module identification";
        postcode_wcktrain       = 0x6233 "3b GDDR WCK training";
        postcode_cdrdtrain      = 0x4333 "3C GDDR read training with CDR enabled";
        postcode_cdretrain      = 0x6433 "3d GDDR Read Training with CDR disabled";
        postcode_wrtrain        = 0x4533 "3E GDDR Write Training";
        postcode_fintrain       = 0x4633 "3F Finalize GDDR Training";
        postcode_osauth         = 0x3034 "40 Begin Coprocessor OS authentification";
        postcode_loading0       = 0x3035 "50 Coprocessor OS Loading 0";
        postcode_loading1       = 0x3135 "51 Coprocessor OS Loading 1";
        postcode_loading2       = 0x3235 "52 Coprocessor OS Loading 2";
        postcode_loading3       = 0x3335 "53 Coprocessor OS Loading 3";
        postcode_loading4       = 0x3435 "54 Coprocessor OS Loading 4";
        postcode_loading5       = 0x3535 "55 Coprocessor OS Loading 5";
        postcode_loading6       = 0x3635 "56 Coprocessor OS Loading 6";
        postcode_loading7       = 0x3735 "57 Coprocessor OS Loading 7";
        postcode_loading8       = 0x3835 "58 Coprocessor OS Loading 8";
        postcode_loading9       = 0x3935 "59 Coprocessor OS Loading 9";
        postcode_loadingb       = 0x4135 "5A Coprocessor OS Loading A";
        postcode_loadinga       = 0x4235 "5B Coprocessor OS Loading B";
        postcode_loadingc       = 0x4335 "5C Coprocessor OS Loading C";
        postcode_loadingd       = 0x4435 "5D Coprocessor OS Loading D";
        postcode_loadinge       = 0x4535 "5E Coprocessor OS Loading E";
        postcode_loadingf       = 0x4635 "5F Coprocessor OS Loading F";
        postcode_gp             = 0x5036 "6P Int 13 - General Protection Fault";
        postcode_tss            = 0x3537 "75 Int 10 - Invalid TSS";
        postcode_fpu            = 0x3738 "87 Int 16 - x87 FPU Error";
        postcode_algin          = 0x4341 "AC INT 17 - Alignment Check";
        postcode_bp             = 0x5062 "bP INT 3 - Break Point";
        postcode_bound          = 0x7262 "br INT 5 - BOUND Range Exceeded";
        postcode_mc             = 0x4343 "CC INT 18 - Machine Check";
        postcode_seg            = 0x6F63 "co INT 9 - Coprocessor Segmenet Overrun";
        postcode_dbg            = 0x6264 "db INT 1 - Debug";
        postcode_div            = 0x4564 "dE INT 0 - Divide Error";
        postcode_df             = 0x4664 "dF INT 8 - Double Fault";
        postcode_memf           = 0x4545 "EE Memory Test Failed";
        postcode_pnf            = 0x3046 "F0 GDDR Parameters not found";
        postcode_pllf           = 0x3146 "F1 GBOX PLL lock failure";
        postcode_memtf          = 0x3246 "F2 GDDR failed memory training";
        postcode_memqf          = 0x3346 "F3 GDDR memory module query failed";
        postcode_mempf          = 0x3446 "F4 Memory preservation failure";
        postcode_sf             = 0x3546 "F5 INT 12 - Stack Fault";
        postcode_done           = 0x4646 "FF - Bootstrap finished execution";
        postcode_ld             = 0x644C "Ld - Locking down hardware access";
        postcode_authf          = 0x416E "nA - OS Image failed Authentification";
        postcode_dna            = 0x646E "nd INT 7 - Device not Available";
        postcode_nmi            = 0x6F6E "no INT 2 - Non-maskable Interrupt";
        postcode_snp            = 0x506E "nP INT 11 - Segment Not Present";
        postcode_of             = 0x466F "oF INT 4 - Overflow";
        postcode_pf             = 0x4650 "PF INT 14 - Pagefault";
        postcode_rs             = 0x3572 "r5 INT 15 - Reserved";
        postcode_iop            = 0x6475 "ud INT 6 - Invalid OP code";
        postcode_unknownerr	    = 0x3048 "H0 Unknown Error, HALT";
    };
    
    constants postcodes_special width(32) "The Xeon Phi Post codes" {
        postcode_invalid = 0x0;
        postcode_fatal   = 0xffffffff;
    };
    
    
    register postcode rw addr(dbox_base, 0x242c) {
        code  16 type(postcodes);
        _     16;
    };
    
    register postcode_raw rw also addr(dbox_base, 0x242c) {
        code0  8;
        code1  8;
        _     16;
    };

};

