/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_ivahd_cm2.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_ivahd_cm2 msbfirst ( addr base ) "" {
    

    constants clkactivity_ivahd_clk_status width(1) "" {
        CLKACTIVITY_IVAHD_CLK_0_r = 0 "Corresponding clock is definitely gated";
        CLKACTIVITY_IVAHD_CLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
    };

    constants clktrctrl_status width(2) "" {
        CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
        CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
        CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
        CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
    };
    
    register cm_ivahd_clkstctrl addr(base, 0x0) "This register enables the IVAHD domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
        _ 23 mbz;
        clkactivity_ivahd_clk 1 ro type(clkactivity_ivahd_clk_status) "This field indicates the state of the IVAHD_CLK clock input of the domain. [warm reset insensitive]";
        _ 6 mbz;
        clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the IVAHD clock domain.";
    };

    constants l3_2_statdep_status width(1) "" {
        L3_2_STATDEP_1_r = 1 "Dependency is enabled";
    };

    constants l3_1_statdep_status width(1) "" {
        L3_1_STATDEP_0 = 0 "Dependency is disabled";
        L3_1_STATDEP_1 = 1 "Dependency is enabled";
    };
    
    register cm_ivahd_staticdep addr(base, 0x4) "This register controls the static domain depedencies from IVAHD domain towards 'target' domains. It is relevant only for domain having system initiator(s)." {
        _ 25 mbz;
        l3_2_statdep 1 ro type(l3_2_statdep_status) "Static dependency towards L3_2 clock domain";
        l3_1_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards L3_1 clock domain";
        memif_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards MEMIF clock domain";
        _ 4 mbz;
    };
    
    register cm_ivahd_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from IVAHD domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." {
        _ 25 mbz;
        l3_2_dyndep 1 ro type(l3_1_statdep_status) "Dynamic dependency towards L3_2 clock domain";
        _ 6 mbz;
    };

    constants stbyst_status width(1) "" {
        STBYST_0_r = 0 "Module is functional (not in standby)";
        STBYST_1_r = 1 "Module is in standby";
    };

    constants idlest_status width(2) "" {
        IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
        IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
        IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
        IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
    };

    constants modulemode_status width(2) "" {
        MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
        MODULEMODE_1 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state.";
        MODULEMODE_2_r = 2 "Reserved";
        MODULEMODE_3_r = 3 "Reserved";
    };
    
    register cm_ivahd_ivahd_clkctrl addr(base, 0x20) "This register manages the IVAHD clocks." {
        _ 13 mbz;
        stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
    };
    
    register cm_ivahd_sl2_clkctrl addr(base, 0x28) "This register manages the SL2 clocks." {
        _ 14 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
    };
};